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[209.51.188.17]) by mx.google.com with ESMTPS id iv15si9119qvb.64.2021.10.07.10.52.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Oct 2021 10:52:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Q4BrtGvX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:32818 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mYXZO-0002XZ-Rp for patch@linaro.org; Thu, 07 Oct 2021 13:52:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mYXUY-000445-Ap for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:42 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:42744) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mYXUU-0006w0-SC for qemu-devel@nongnu.org; Thu, 07 Oct 2021 13:47:38 -0400 Received: by mail-pl1-x636.google.com with SMTP id l6so4378779plh.9 for ; Thu, 07 Oct 2021 10:47:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vZLRJy8/jxA2VUmbIFcOC3CPI+naiU5qep1MI8LkbwQ=; b=Q4BrtGvXKnX/ujXqGxKCkAksE5Fw1FmhYITG69nWjvXz1j1JYhm84BGCUCVfHoUjfh 6C670soZKysgs6FeL3y03hYCsAdnwkuKS3i6EBBcL/Ruox0kyAbkRIkgOCpgol+3YYA7 dSpCZWLrNW94iVndyzajP1gRs8G/9idNsn4X+XzMt73DdO0Yvgc1kiKMpfAGlmBqnPET fX/aiaINe0eQ5lXk/DjWa6bi2mNGIQ+BfGOmRGwmoS9dYeBtJ8/EOY4eE+ezya2Ee/U2 3t83pgIjpuKSd/uhoihhGP/7AT9rO1T4WWJgJ9sTzxVsOTbdN55zx/PXIAOdULwrwtBL KCiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vZLRJy8/jxA2VUmbIFcOC3CPI+naiU5qep1MI8LkbwQ=; b=39AjdXIzatKGK/7UR9k92TP2P3vgC+0xA5pqlPejHHJGuKm/Lm8xtI5fg9vygCY3ol l84Ge81z9uZ2F+QvOy7DD+UQgLQRP0cqW+IdyFGf7Zuw7IhOF9mJIWkoqf6TrhVHVmN9 OS9SdZ+WUCtEsC9XVYOiztEWlCuf2On1uVOEhx2DOh1suL7tUO9LMwWsnOGSH7qdrshC X7Z1MDNgeL+3sVb1bsI2jZK7XFJdN7i8kbrQXs/55y7Lj1QvTE6zBw9GszJDDOxfHc8b w2S3WbL/IzwiNrgeW3Wq9zNhi/bTSpybNAssaaHPeEik/YEZwxRYx9dJQD6itVY8umnK zfLg== X-Gm-Message-State: AOAM532gVseT0q5hVKThLeKwx4w3g226AQvFocxc7jMdBuQwhWf9uv6U VtGDz5ixprcBZOn+Ie2QwVjTX1WaFN/wwg== X-Received: by 2002:a17:90a:4306:: with SMTP id q6mr6931896pjg.202.1633628852086; Thu, 07 Oct 2021 10:47:32 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 197sm83318pfv.6.2021.10.07.10.47.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 10:47:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Date: Thu, 7 Oct 2021 10:47:20 -0700 Message-Id: <20211007174722.929993-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org> References: <20211007174722.929993-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr, qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When target_long is 64-bit, we still want a 32-bit bswap for rev8. Since this opcode is specific to RV32, we need not conditionalize. Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.25.1 Reviewed-by: LIU Zhiwei diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 66dd51de49..c62eea433a 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a) return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl); } +static void gen_rev8_32(TCGv ret, TCGv src1) +{ + tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS); +} + static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a) { REQUIRE_32BIT(ctx); REQUIRE_ZBB(ctx); - return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl); + return gen_unary(ctx, a, EXT_NONE, gen_rev8_32); } static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)