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[24.74.129.96]) by smtp.gmail.com with ESMTPSA id r13sm7141104qkk.73.2021.09.24.09.59.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Sep 2021 09:59:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 16/27] linux-user/nios2: Properly emulate EXCP_TRAP Date: Fri, 24 Sep 2021 12:59:15 -0400 Message-Id: <20210924165926.752809-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210924165926.752809-1-richard.henderson@linaro.org> References: <20210924165926.752809-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f34; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The real kernel has to load the instruction and extract the imm5 field; for qemu, modify the translator to do this. The use of R_AT for this in cpu_loop was a bug. Handle the other trap numbers as per the kernel's trap_table. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 5 +++-- linux-user/nios2/cpu_loop.c | 35 ++++++++++++++++++----------------- target/nios2/translate.c | 17 ++++++++++++++++- 3 files changed, 37 insertions(+), 20 deletions(-) -- 2.25.1 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2ab82fdc71..395e4d3281 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -158,9 +158,10 @@ struct Nios2CPUClass { struct CPUNios2State { uint32_t regs[NUM_CORE_REGS]; -#if !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY + int trap_code; +#else Nios2MMU mmu; - uint32_t irq_pending; #endif }; diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 34290fb3b5..246293a501 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -39,9 +39,10 @@ void cpu_loop(CPUNios2State *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; + case EXCP_TRAP: - if (env->regs[R_AT] == 0) { - abi_long ret; + switch (env->trap_code) { + case 0: qemu_log_mask(CPU_LOG_INT, "\nSyscall\n"); ret = do_syscall(env, env->regs[2], @@ -55,26 +56,26 @@ void cpu_loop(CPUNios2State *env) env->regs[2] = abs(ret); /* Return value is 0..4096 */ - env->regs[7] = (ret > 0xfffffffffffff000ULL); - env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; - env->regs[CR_STATUS] &= ~0x3; - env->regs[R_EA] = env->regs[R_PC] + 4; + env->regs[7] = ret > 0xfffff000u; env->regs[R_PC] += 4; break; - } else { - qemu_log_mask(CPU_LOG_INT, "\nTrap\n"); - env->regs[CR_ESTATUS] = env->regs[CR_STATUS]; - env->regs[CR_STATUS] &= ~0x3; - env->regs[R_EA] = env->regs[R_PC] + 4; - env->regs[R_PC] = cpu->exception_addr; - - info.si_signo = TARGET_SIGTRAP; - info.si_errno = 0; - info.si_code = TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + case 1: + qemu_log_mask(CPU_LOG_INT, "\nTrap 1\n"); + force_sig_fault(TARGET_SIGUSR1, 0, env->regs[R_PC]); + break; + case 2: + qemu_log_mask(CPU_LOG_INT, "\nTrap 2\n"); + force_sig_fault(TARGET_SIGUSR2, 0, env->regs[R_PC]); + break; + default: + qemu_log_mask(CPU_LOG_INT, "\nTrap %d\n", env->trap_code); + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, + env->regs[R_PC]); break; } + break; + case EXCP_DEBUG: info.si_signo = TARGET_SIGTRAP; info.si_errno = 0; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 08d7ac5398..485b487665 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -636,6 +636,21 @@ static void divu(DisasContext *dc, uint32_t code, uint32_t flags) tcg_temp_free(t0); } +static void trap(DisasContext *dc, uint32_t code, uint32_t flags) +{ +#ifdef CONFIG_USER_ONLY + /* + * The imm5 field is not stored anywhere on real hw; the kernel + * has to load the insn and extract the field. But we can make + * things easier for cpu_loop if we pop this into env->trap_code. + */ + R_TYPE(instr, code); + tcg_gen_st_i32(tcg_constant_i32(instr.imm5), cpu_env, + offsetof(CPUNios2State, trap_code)); +#endif + t_gen_helper_raise_exception(dc, EXCP_TRAP); +} + static const Nios2Instruction r_type_instructions[] = { INSTRUCTION_ILLEGAL(), INSTRUCTION(eret), /* eret */ @@ -682,7 +697,7 @@ static const Nios2Instruction r_type_instructions[] = { INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(), - INSTRUCTION_FLG(gen_excp, EXCP_TRAP), /* trap */ + INSTRUCTION(trap), /* trap */ INSTRUCTION(wrctl), /* wrctl */ INSTRUCTION_ILLEGAL(), INSTRUCTION_FLG(gen_cmpxx, TCG_COND_LTU), /* cmpltu */