Message ID | 20210916153025.1944763-29-richard.henderson@linaro.org |
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Thu, 16 Sep 2021 08:30:45 -0700 (PDT) From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 28/35] target/sparc: Restrict has_work() handler to sysemu Date: Thu, 16 Sep 2021 08:30:18 -0700 Message-Id: <20210916153025.1944763-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210916153025.1944763-1-richard.henderson@linaro.org> References: <20210916153025.1944763-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org> |
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diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index e83e305aa9..4a63ed1264 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -702,6 +702,7 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, cpu->env.npc = tb->cs_base; } +#if !defined(CONFIG_USER_ONLY) static bool sparc_cpu_has_work(CPUState *cs) { SPARCCPU *cpu = SPARC_CPU(cs); @@ -710,6 +711,7 @@ static bool sparc_cpu_has_work(CPUState *cs) return (cs->interrupt_request & CPU_INTERRUPT_HARD) && cpu_interrupts_enabled(env); } +#endif /* !CONFIG_USER_ONLY */ static char *sparc_cpu_type_name(const char *cpu_model) { @@ -867,6 +869,7 @@ static const struct TCGCPUOps sparc_tcg_ops = { .tlb_fill = sparc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = sparc_cpu_has_work, .cpu_exec_interrupt = sparc_cpu_exec_interrupt, .do_interrupt = sparc_cpu_do_interrupt, .do_transaction_failed = sparc_cpu_do_transaction_failed, @@ -888,7 +891,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = sparc_cpu_class_by_name; cc->parse_features = sparc_cpu_parse_features; - cc->has_work = sparc_cpu_has_work; cc->dump_state = sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug = sparc_cpu_memory_rw_debug;