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[82.27.106.168]) by smtp.gmail.com with ESMTPSA id k6sm184252wmo.37.2021.09.14.07.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Sep 2021 07:24:26 -0700 (PDT) From: Jean-Philippe Brucker To: eric.auger@redhat.com Subject: [PATCH v3 05/10] pc: Allow instantiating a virtio-iommu device Date: Tue, 14 Sep 2021 15:20:00 +0100 Message-Id: <20210914142004.2433568-6-jean-philippe@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210914142004.2433568-1-jean-philippe@linaro.org> References: <20210914142004.2433568-1-jean-philippe@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=jean-philippe@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ehabkost@redhat.com, mst@redhat.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, shannon.zhaosl@gmail.com, Jean-Philippe Brucker , qemu-arm@nongnu.org, pbonzini@redhat.com, ani@anisinha.ca, imammedo@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Allow instantiating a virtio-iommu device by adding an ACPI Virtual I/O Translation table (VIOT), which describes the relation between the virtio-iommu and the endpoints it manages. Add a hotplug handler for virtio-iommu on x86 and set the necessary reserved region property. On x86, the [0xfee00000, 0xfeefffff] DMA region is reserved for MSIs. DMA transactions to this range either trigger IRQ remapping in the IOMMU or bypasses IOMMU translation. Although virtio-iommu does not support IRQ remapping it must be informed of the reserved region so that it can forward DMA transactions targeting this region. Signed-off-by: Jean-Philippe Brucker --- include/hw/i386/pc.h | 2 ++ hw/i386/acpi-build.c | 5 +++++ hw/i386/pc.c | 28 +++++++++++++++++++++++++++- hw/i386/Kconfig | 1 + 4 files changed, 35 insertions(+), 1 deletion(-) -- 2.33.0 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 82cf7b7e30..f3ba1ee4c0 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -45,6 +45,8 @@ typedef struct PCMachineState { bool pit_enabled; bool hpet_enabled; bool default_bus_bypass_iommu; + bool virtio_iommu; + uint16_t virtio_iommu_bdf; uint64_t max_fw_size; /* ACPI Memory hotplug IO base address */ diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 547cd4ed9d..76845026d8 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -71,6 +71,7 @@ #include "hw/acpi/ipmi.h" #include "hw/acpi/hmat.h" +#include "hw/acpi/viot.h" /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows @@ -2593,6 +2594,10 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine) build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); } + } else if (pcms->virtio_iommu) { + acpi_add_table(table_offsets, tables_blob); + build_viot(tables_blob, tables->linker, pcms->virtio_iommu_bdf, + x86ms->oem_id, x86ms->oem_table_id); } if (machine->nvdimms_state->is_enabled) { nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 7e523b913c..a31e950599 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -83,6 +83,7 @@ #include "hw/i386/intel_iommu.h" #include "hw/net/ne2000-isa.h" #include "standard-headers/asm-x86/bootparam.h" +#include "hw/virtio/virtio-iommu.h" #include "hw/virtio/virtio-pmem-pci.h" #include "hw/virtio/virtio-mem-pci.h" #include "hw/mem/memory-device.h" @@ -798,6 +799,11 @@ void pc_machine_done(Notifier *notifier, void *data) "irqchip support."); exit(EXIT_FAILURE); } + + if (pcms->virtio_iommu && x86_iommu_get_default()) { + error_report("QEMU does not support multiple vIOMMUs for x86 yet."); + exit(EXIT_FAILURE); + } } void pc_guest_info_init(PCMachineState *pcms) @@ -1368,6 +1374,14 @@ static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { + /* Declare the reserved MSI region */ + char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", + VIRTIO_IOMMU_RESV_MEM_T_MSI); + + qdev_prop_set_uint32(dev, "len-reserved-regions", 1); + qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str); + g_free(resv_prop_str); } } @@ -1381,6 +1395,17 @@ static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { pc_virtio_md_pci_plug(hotplug_dev, dev, errp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { + PCMachineState *pcms = PC_MACHINE(hotplug_dev); + PCIDevice *pdev = PCI_DEVICE(dev); + + if (pcms->virtio_iommu) { + error_setg(errp, + "QEMU does not support multiple vIOMMUs for x86 yet."); + return; + } + pcms->virtio_iommu = true; + pcms->virtio_iommu_bdf = pci_get_bdf(pdev); } } @@ -1422,7 +1447,8 @@ static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || object_dynamic_cast(OBJECT(dev), TYPE_CPU) || object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || - object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { + object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || + object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { return HOTPLUG_HANDLER(machine); } diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index ddedcef0b2..13db05d557 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -54,6 +54,7 @@ config PC_ACPI select ACPI_X86 select ACPI_CPU_HOTPLUG select ACPI_MEMORY_HOTPLUG + select ACPI_VIOT select SMBUS_EEPROM select PFLASH_CFI01 depends on ACPI_SMBUS