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Mon, 13 Sep 2021 17:18:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 43/44] tcg/arm: More use of the ARMInsn enum Date: Mon, 13 Sep 2021 17:14:55 -0700 Message-Id: <20210914001456.793490-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index c068e707e8..cf0627448b 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -570,7 +570,7 @@ static void tcg_out_blx_imm(TCGContext *s, int32_t offset) (((offset - 8) >> 2) & 0x00ffffff)); } -static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, int opc, int rd, +static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc, int rd, int rn, int rm, int shift) { tcg_out32(s, (cond << 28) | (0 << 25) | opc | @@ -603,14 +603,14 @@ static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn) } } -static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, int opc, +static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc, int rd, int rn, int im) { tcg_out32(s, (cond << 28) | (1 << 25) | opc | (rn << 16) | (rd << 12) | im); } -static void tcg_out_ldstm(TCGContext *s, ARMCond cond, int opc, +static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rn, uint16_t mask) { tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask); @@ -637,8 +637,8 @@ static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); } -static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt, - TCGReg rn, int imm12, bool p, bool w) +static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc, + TCGReg rt, TCGReg rn, int imm12, bool p, bool w) { bool u = 1; if (imm12 < 0) { @@ -873,7 +873,7 @@ static void tcg_out_movi32(TCGContext *s, ARMCond cond, int rd, uint32_t arg) * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rI" constraint. */ -static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, int opc, TCGArg dst, +static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc, TCGArg dst, TCGArg lhs, TCGArg rhs, int rhs_is_const) { if (rhs_is_const) { @@ -887,8 +887,8 @@ static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, int opc, TCGArg dst, * Emit either the reg,imm or reg,reg form of a data-processing insn. * rhs must satisfy the "rIK" constraint. */ -static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, int opc, int opinv, - TCGReg dst, TCGReg lhs, TCGArg rhs, +static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc, + ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs, bool rhs_is_const) { if (rhs_is_const) { @@ -903,8 +903,8 @@ static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, int opc, int opinv, } } -static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, int opc, int opneg, - TCGArg dst, TCGArg lhs, TCGArg rhs, +static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc, + ARMInsn opneg, TCGArg dst, TCGArg lhs, TCGArg rhs, bool rhs_is_const) { /* Emit either the reg,imm or reg,reg form of a data-processing insn.