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[PULL,11/44] target/i386: Simplify TARGET_X86_64 #ifdef'ry

Message ID	20210914001456.793490-12-richard.henderson@linaro.org
State	Accepted
Commit	30ca39244bccc93d90a9a763e7e3d115ba089c13
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 11/44] target/i386: Simplify TARGET_X86_64 #ifdef'ry Date: Mon, 13 Sep 2021 17:14:23 -0700 Message-Id: <20210914001456.793490-12-richard.henderson@linaro.org> In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org> References: <20210914001456.793490-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>, Warner Losh <imp@bsdimp.com> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg patch queue, v2 \| expand [PULL,00/44] tcg patch queue, v2 [PULL,01/44] accel/tcg: Add DisasContextBase argument to translator_ld* [PULL,02/44] accel/tcg: Clear PAGE_WRITE before translation [PULL,03/44] tcg/i386: Split P_VEXW from P_REXW [PULL,04/44] accel/tcg: remove redundant TCG_KICK_PERIOD define [PULL,05/44] tcg: Remove tcg_global_reg_new defines [PULL,06/44] tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN [PULL,07/44] tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF [PULL,08/44] tcg/arm: Fix tcg_out_vec_op function signature [PULL,09/44] target/avr: Remove pointless use of CONFIG_USER_ONLY definition [PULL,10/44] target/i386: Restrict sysemu-only fpu_helper helpers [PULL,11/44] target/i386: Simplify TARGET_X86_64 #ifdef'ry [PULL,12/44] target/xtensa: Restrict do_transaction_failed() to sysemu [PULL,13/44] accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt [PULL,14/44] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu [PULL,15/44] target/arm: Restrict cpu_exec_interrupt() handler to sysemu [PULL,16/44] target/cris: Restrict cpu_exec_interrupt() handler to sysemu [PULL,17/44] target/hppa: Restrict cpu_exec_interrupt() handler to sysemu [PULL,18/44] target/i386: Restrict cpu_exec_interrupt() handler to sysemu [PULL,19/44] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder [PULL,20/44] target/m68k: Restrict cpu_exec_interrupt() handler to sysemu [PULL,21/44] target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu [PULL,22/44] target/mips: Restrict cpu_exec_interrupt() handler to sysemu [PULL,23/44] target/nios2: Restrict cpu_exec_interrupt() handler to sysemu [PULL,24/44] target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu [PULL,25/44] target/ppc: Restrict cpu_exec_interrupt() handler to sysemu [PULL,26/44] target/riscv: Restrict cpu_exec_interrupt() handler to sysemu [PULL,27/44] target/sh4: Restrict cpu_exec_interrupt() handler to sysemu [PULL,28/44] target/sparc: Restrict cpu_exec_interrupt() handler to sysemu [PULL,29/44] target/rx: Restrict cpu_exec_interrupt() handler to sysemu [PULL,30/44] target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu [PULL,31/44] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu [PULL,32/44] user: Remove cpu_get_pic_interrupt() stubs [PULL,33/44] user: Mark cpu_loop() with noreturn attribute [PULL,34/44] accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts [PULL,35/44] tcg/arm: Remove fallback definition of __ARM_ARCH [PULL,36/44] tcg/arm: Standardize on tcg_out_<branch>_{reg,imm} [PULL,37/44] tcg/arm: Simplify use_armv5t_instructions [PULL,38/44] tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call [PULL,39/44] tcg/arm: Split out tcg_out_ldstm [PULL,40/44] tcg/arm: Simplify usage of encode_imm [PULL,41/44] tcg/arm: Drop inline markers [PULL,42/44] tcg/arm: Give enum arm_cond_code_e a typedef and use it [PULL,43/44] tcg/arm: More use of the ARMInsn enum [PULL,44/44] tcg/arm: More use of the TCGReg enum

Commit Message

Richard Henderson Sept. 14, 2021, 12:14 a.m. UTC

From: Philippe Mathieu-Daudé <f4bug@amsat.org>


Merge two TARGET_X86_64 consecutive blocks.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Warner Losh <imp@bsdimp.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-Id: <20210911165434.531552-4-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/i386/tcg/seg_helper.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

-- 
2.25.1

diff mbox series

Patch

diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index cef68b610a..56263e358d 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -929,9 +929,7 @@  static void do_interrupt64(CPUX86State *env, int intno, int is_int,
                    e2);
     env->eip = offset;
 }
-#endif
 
-#ifdef TARGET_X86_64
 void helper_sysret(CPUX86State *env, int dflag)
 {
     int cpl, selector;
@@ -984,7 +982,7 @@  void helper_sysret(CPUX86State *env, int dflag)
                                DESC_W_MASK | DESC_A_MASK);
     }
 }
-#endif
+#endif /* TARGET_X86_64 */
 
 /* real mode interrupt */
 static void do_interrupt_real(CPUX86State *env, int intno, int is_int,