| Message ID | 20210913220552.604064-2-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | linux-user: Streamline handling of SIGSEGV/SIGBUS | expand |
On 9/14/21 12:05 AM, Richard Henderson wrote: > There is nothing target specific about this. The implementation > is host specific, but the declaration is 100% common. Same as v3 ;) https://www.mail-archive.com/qemu-devel@nongnu.org/msg830412.html Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > include/exec/exec-all.h | 13 +++++++++++++ > target/alpha/cpu.h | 6 ------ > target/arm/cpu.h | 7 ------- > target/avr/cpu.h | 2 -- > target/cris/cpu.h | 8 -------- > target/hexagon/cpu.h | 3 --- > target/hppa/cpu.h | 3 --- > target/i386/cpu.h | 7 ------- > target/m68k/cpu.h | 8 -------- > target/microblaze/cpu.h | 7 ------- > target/mips/cpu.h | 3 --- > target/mips/internal.h | 2 -- > target/nios2/cpu.h | 2 -- > target/openrisc/cpu.h | 2 -- > target/ppc/cpu.h | 7 ------- > target/riscv/cpu.h | 2 -- > target/rx/cpu.h | 4 ---- > target/s390x/cpu.h | 7 ------- > target/sh4/cpu.h | 3 --- > target/sparc/cpu.h | 2 -- > target/tricore/cpu.h | 2 -- > target/xtensa/cpu.h | 2 -- > 22 files changed, 13 insertions(+), 89 deletions(-)
On Mon, Sep 13, 2021 at 4:05 PM Richard Henderson < richard.henderson@linaro.org> wrote: > There is nothing target specific about this. The implementation > is host specific, but the declaration is 100% common. > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > include/exec/exec-all.h | 13 +++++++++++++ > target/alpha/cpu.h | 6 ------ > target/arm/cpu.h | 7 ------- > target/avr/cpu.h | 2 -- > target/cris/cpu.h | 8 -------- > target/hexagon/cpu.h | 3 --- > target/hppa/cpu.h | 3 --- > target/i386/cpu.h | 7 ------- > target/m68k/cpu.h | 8 -------- > target/microblaze/cpu.h | 7 ------- > target/mips/cpu.h | 3 --- > target/mips/internal.h | 2 -- > target/nios2/cpu.h | 2 -- > target/openrisc/cpu.h | 2 -- > target/ppc/cpu.h | 7 ------- > target/riscv/cpu.h | 2 -- > target/rx/cpu.h | 4 ---- > target/s390x/cpu.h | 7 ------- > target/sh4/cpu.h | 3 --- > target/sparc/cpu.h | 2 -- > target/tricore/cpu.h | 2 -- > target/xtensa/cpu.h | 2 -- > 22 files changed, 13 insertions(+), 89 deletions(-) > Reviewed-By: Warner Losh <imp@bsdimp.com> Warner > diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h > index 5d1b6d80fb..9d5987ba04 100644 > --- a/include/exec/exec-all.h > +++ b/include/exec/exec-all.h > @@ -662,6 +662,19 @@ static inline tb_page_addr_t > get_page_addr_code_hostp(CPUArchState *env, > } > return addr; > } > + > +/** > + * cpu_signal_handler > + * @signum: host signal number > + * @pinfo: host siginfo_t > + * @puc: host ucontext_t > + * > + * To be called from the SIGBUS and SIGSEGV signal handler to inform the > + * virtual cpu of exceptions. Returns true if the signal was handled by > + * the virtual CPU. > + */ > +int cpu_signal_handler(int signum, void *pinfo, void *puc); > + > #else > static inline void mmap_lock(void) {} > static inline void mmap_unlock(void) {} > diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h > index 4e993bd15b..ce9ec32199 100644 > --- a/target/alpha/cpu.h > +++ b/target/alpha/cpu.h > @@ -287,7 +287,6 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, > vaddr addr, > int mmu_idx, uintptr_t retaddr); > > #define cpu_list alpha_cpu_list > -#define cpu_signal_handler cpu_alpha_signal_handler > > typedef CPUAlphaState CPUArchState; > typedef AlphaCPU ArchCPU; > @@ -440,11 +439,6 @@ void alpha_translate_init(void); > #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU > > void alpha_cpu_list(void); > -/* you can call this signal handler from your SIGBUS and SIGSEGV > - signal handlers to inform the virtual CPU of exceptions. non zero > - is returned if the signal was handled by the virtual CPU. */ > -int cpu_alpha_signal_handler(int host_signum, void *pinfo, > - void *puc); > bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > MMUAccessType access_type, int mmu_idx, > bool probe, uintptr_t retaddr); > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index cfd755cff9..6c78957e54 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1121,12 +1121,6 @@ static inline bool is_a64(CPUARMState *env) > return env->aarch64; > } > > -/* you can call this signal handler from your SIGBUS and SIGSEGV > - signal handlers to inform the virtual CPU of exceptions. non zero > - is returned if the signal was handled by the virtual CPU. */ > -int cpu_arm_signal_handler(int host_signum, void *pinfo, > - void *puc); > - > /** > * pmu_op_start/finish > * @env: CPUARMState > @@ -3015,7 +3009,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool > kvm_sync); > #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) > #define CPU_RESOLVING_TYPE TYPE_ARM_CPU > > -#define cpu_signal_handler cpu_arm_signal_handler > #define cpu_list arm_cpu_list > > /* ARM has the following "translation regimes" (as the ARM ARM calls > them): > diff --git a/target/avr/cpu.h b/target/avr/cpu.h > index 93e3faa0a9..dceacf3cd7 100644 > --- a/target/avr/cpu.h > +++ b/target/avr/cpu.h > @@ -175,7 +175,6 @@ static inline void set_avr_feature(CPUAVRState *env, > int feature) > } > > #define cpu_list avr_cpu_list > -#define cpu_signal_handler cpu_avr_signal_handler > #define cpu_mmu_index avr_cpu_mmu_index > > static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) > @@ -187,7 +186,6 @@ void avr_cpu_tcg_init(void); > > void avr_cpu_list(void); > int cpu_avr_exec(CPUState *cpu); > -int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc); > int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, > int len, bool is_write); > > diff --git a/target/cris/cpu.h b/target/cris/cpu.h > index be021899ae..6603565f83 100644 > --- a/target/cris/cpu.h > +++ b/target/cris/cpu.h > @@ -199,12 +199,6 @@ int crisv10_cpu_gdb_read_register(CPUState *cpu, > GByteArray *buf, int reg); > int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > > -/* you can call this signal handler from your SIGBUS and SIGSEGV > - signal handlers to inform the virtual CPU of exceptions. non zero > - is returned if the signal was handled by the virtual CPU. */ > -int cpu_cris_signal_handler(int host_signum, void *pinfo, > - void *puc); > - > void cris_initialize_tcg(void); > void cris_initialize_crisv10_tcg(void); > > @@ -250,8 +244,6 @@ enum { > #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) > #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU > > -#define cpu_signal_handler cpu_cris_signal_handler > - > /* MMU modes definitions */ > #define MMU_USER_IDX 1 > static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) > diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h > index 2855dd3881..f7d043865b 100644 > --- a/target/hexagon/cpu.h > +++ b/target/hexagon/cpu.h > @@ -129,9 +129,6 @@ typedef struct HexagonCPU { > > #include "cpu_bits.h" > > -#define cpu_signal_handler cpu_hexagon_signal_handler > -int cpu_hexagon_signal_handler(int host_signum, void *pinfo, void *puc); > - > static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, > target_ulong *pc, > target_ulong *cs_base, uint32_t > *flags) > { > diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h > index 7854675b90..d3cb7a279f 100644 > --- a/target/hppa/cpu.h > +++ b/target/hppa/cpu.h > @@ -319,9 +319,6 @@ static inline void > cpu_hppa_change_prot_id(CPUHPPAState *env) { } > void cpu_hppa_change_prot_id(CPUHPPAState *env); > #endif > > -#define cpu_signal_handler cpu_hppa_signal_handler > - > -int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); > hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); > int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 7dd664791a..c2954c71ea 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -1947,12 +1947,6 @@ void cpu_x86_frstor(CPUX86State *s, target_ulong > ptr, int data32); > void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); > void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); > > -/* you can call this signal handler from your SIGBUS and SIGSEGV > - signal handlers to inform the virtual CPU of exceptions. non zero > - is returned if the signal was handled by the virtual CPU. */ > -int cpu_x86_signal_handler(int host_signum, void *pinfo, > - void *puc); > - > /* cpu.c */ > void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, > uint32_t vendor2, uint32_t vendor3); > @@ -2020,7 +2014,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); > #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") > #endif > > -#define cpu_signal_handler cpu_x86_signal_handler > #define cpu_list x86_cpu_list > > /* MMU modes definitions */ > diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h > index 550eb028b6..a3423729ef 100644 > --- a/target/m68k/cpu.h > +++ b/target/m68k/cpu.h > @@ -177,13 +177,6 @@ int m68k_cpu_gdb_write_register(CPUState *cpu, > uint8_t *buf, int reg); > > void m68k_tcg_init(void); > void m68k_cpu_init_gdb(M68kCPU *cpu); > -/* > - * you can call this signal handler from your SIGBUS and SIGSEGV > - * signal handlers to inform the virtual CPU of exceptions. non zero > - * is returned if the signal was handled by the virtual CPU. > - */ > -int cpu_m68k_signal_handler(int host_signum, void *pinfo, > - void *puc); > uint32_t cpu_m68k_get_ccr(CPUM68KState *env); > void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); > void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); > @@ -563,7 +556,6 @@ enum { > #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX > #define CPU_RESOLVING_TYPE TYPE_M68K_CPU > > -#define cpu_signal_handler cpu_m68k_signal_handler > #define cpu_list m68k_cpu_list > > /* MMU modes definitions */ > diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h > index 40401c33b7..13ed3cd4dd 100644 > --- a/target/microblaze/cpu.h > +++ b/target/microblaze/cpu.h > @@ -385,16 +385,9 @@ static inline void mb_cpu_write_msr(CPUMBState *env, > uint32_t val) > } > > void mb_tcg_init(void); > -/* you can call this signal handler from your SIGBUS and SIGSEGV > - signal handlers to inform the virtual CPU of exceptions. non zero > - is returned if the signal was handled by the virtual CPU. */ > -int cpu_mb_signal_handler(int host_signum, void *pinfo, > - void *puc); > > #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU > > -#define cpu_signal_handler cpu_mb_signal_handler > - > /* MMU modes definitions */ > #define MMU_NOMMU_IDX 0 > #define MMU_KERNEL_IDX 1 > diff --git a/target/mips/cpu.h b/target/mips/cpu.h > index 1dfe69c6c0..56b1cbd091 100644 > --- a/target/mips/cpu.h > +++ b/target/mips/cpu.h > @@ -1193,7 +1193,6 @@ struct MIPSCPU { > > void mips_cpu_list(void); > > -#define cpu_signal_handler cpu_mips_signal_handler > #define cpu_list mips_cpu_list > > extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); > @@ -1277,8 +1276,6 @@ enum { > */ > #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 > > -int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); > - > #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU > #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX > #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU > diff --git a/target/mips/internal.h b/target/mips/internal.h > index eecdd10116..daddb05fd4 100644 > --- a/target/mips/internal.h > +++ b/target/mips/internal.h > @@ -156,8 +156,6 @@ extern const VMStateDescription vmstate_mips_cpu; > > #endif /* !CONFIG_USER_ONLY */ > > -#define cpu_signal_handler cpu_mips_signal_handler > - > static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) > { > return (env->CP0_Status & (1 << CP0St_IE)) && > diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h > index 2ab82fdc71..88a511209c 100644 > --- a/target/nios2/cpu.h > +++ b/target/nios2/cpu.h > @@ -193,7 +193,6 @@ struct Nios2CPU { > > void nios2_tcg_init(void); > void nios2_cpu_do_interrupt(CPUState *cs); > -int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc); > void dump_mmu(CPUNios2State *env); > void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); > hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); > @@ -206,7 +205,6 @@ void do_nios2_semihosting(CPUNios2State *env); > #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU > > #define cpu_gen_code cpu_nios2_gen_code > -#define cpu_signal_handler cpu_nios2_signal_handler > > #define CPU_SAVE_VERSION 1 > > diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h > index be6df81a81..187a4a114e 100644 > --- a/target/openrisc/cpu.h > +++ b/target/openrisc/cpu.h > @@ -320,11 +320,9 @@ void openrisc_translate_init(void); > bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > MMUAccessType access_type, int mmu_idx, > bool probe, uintptr_t retaddr); > -int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); > int print_insn_or1k(bfd_vma addr, disassemble_info *info); > > #define cpu_list cpu_openrisc_list > -#define cpu_signal_handler cpu_openrisc_signal_handler > > #ifndef CONFIG_USER_ONLY > extern const VMStateDescription vmstate_openrisc_cpu; > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index 362e7c4c5c..01d3773bc7 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -1278,12 +1278,6 @@ extern const VMStateDescription vmstate_ppc_cpu; > > > /*****************************************************************************/ > void ppc_translate_init(void); > -/* > - * you can call this signal handler from your SIGBUS and SIGSEGV > - * signal handlers to inform the virtual CPU of exceptions. non zero > - * is returned if the signal was handled by the virtual CPU. > - */ > -int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc); > bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > MMUAccessType access_type, int mmu_idx, > bool probe, uintptr_t retaddr); > @@ -1371,7 +1365,6 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, > uint32_t val); > #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX > #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU > > -#define cpu_signal_handler cpu_ppc_signal_handler > #define cpu_list ppc_cpu_list > > /* MMU modes definitions */ > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index e735e53e26..465142616a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -356,7 +356,6 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, > hwaddr physaddr, > char *riscv_isa_string(RISCVCPU *cpu); > void riscv_cpu_list(void); > > -#define cpu_signal_handler riscv_cpu_signal_handler > #define cpu_list riscv_cpu_list > #define cpu_mmu_index riscv_cpu_mmu_index > > @@ -372,7 +371,6 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, > uint64_t (*fn)(uint32_t), > void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); > > void riscv_translate_init(void); > -int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); > void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, > uint32_t exception, uintptr_t > pc); > > diff --git a/target/rx/cpu.h b/target/rx/cpu.h > index faa3606f52..4ac71aec37 100644 > --- a/target/rx/cpu.h > +++ b/target/rx/cpu.h > @@ -134,13 +134,9 @@ int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t > *buf, int reg); > hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); > > void rx_translate_init(void); > -int cpu_rx_signal_handler(int host_signum, void *pinfo, > - void *puc); > - > void rx_cpu_list(void); > void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); > > -#define cpu_signal_handler cpu_rx_signal_handler > #define cpu_list rx_cpu_list > > #include "exec/cpu-all.h" > diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h > index b26ae8fff2..3153d053e9 100644 > --- a/target/s390x/cpu.h > +++ b/target/s390x/cpu.h > @@ -809,13 +809,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t > gen, uint8_t ec_ga, > #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) > #define CPU_RESOLVING_TYPE TYPE_S390_CPU > > -/* you can call this signal handler from your SIGBUS and SIGSEGV > - signal handlers to inform the virtual CPU of exceptions. non zero > - is returned if the signal was handled by the virtual CPU. */ > -int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); > -#define cpu_signal_handler cpu_s390x_signal_handler > - > - > /* interrupt.c */ > #define RA_IGNORED 0 > void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t > ra); > diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h > index 017a770214..56f7c32df9 100644 > --- a/target/sh4/cpu.h > +++ b/target/sh4/cpu.h > @@ -213,8 +213,6 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, > vaddr addr, > int mmu_idx, uintptr_t retaddr); > > void sh4_translate_init(void); > -int cpu_sh4_signal_handler(int host_signum, void *pinfo, > - void *puc); > bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > MMUAccessType access_type, int mmu_idx, > bool probe, uintptr_t retaddr); > @@ -250,7 +248,6 @@ void cpu_load_tlb(CPUSH4State * env); > #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX > #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU > > -#define cpu_signal_handler cpu_sh4_signal_handler > #define cpu_list sh4_cpu_list > > /* MMU modes definitions */ > diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h > index ff8ae73002..6b40d02237 100644 > --- a/target/sparc/cpu.h > +++ b/target/sparc/cpu.h > @@ -649,13 +649,11 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, > target_ulong addr, > int mmu_idx); > #endif > #endif > -int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); > > #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU > #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX > #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU > > -#define cpu_signal_handler cpu_sparc_signal_handler > #define cpu_list sparc_cpu_list > > /* MMU modes definitions */ > diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h > index 4b61a2c03f..c461387e71 100644 > --- a/target/tricore/cpu.h > +++ b/target/tricore/cpu.h > @@ -362,7 +362,6 @@ void fpu_set_state(CPUTriCoreState *env); > > void tricore_cpu_list(void); > > -#define cpu_signal_handler cpu_tricore_signal_handler > #define cpu_list tricore_cpu_list > > static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) > @@ -377,7 +376,6 @@ typedef TriCoreCPU ArchCPU; > > void cpu_state_reset(CPUTriCoreState *s); > void tricore_tcg_init(void); > -int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc); > > static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, > target_ulong *pc, > target_ulong *cs_base, uint32_t > *flags) > diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h > index cbb720e7cc..646965f379 100644 > --- a/target/xtensa/cpu.h > +++ b/target/xtensa/cpu.h > @@ -584,7 +584,6 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, > vaddr addr, > MMUAccessType access_type, > int mmu_idx, uintptr_t retaddr); > > -#define cpu_signal_handler cpu_xtensa_signal_handler > #define cpu_list xtensa_cpu_list > > #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU > @@ -613,7 +612,6 @@ void check_interrupts(CPUXtensaState *s); > void xtensa_irq_init(CPUXtensaState *env); > qemu_irq *xtensa_get_extints(CPUXtensaState *env); > qemu_irq xtensa_get_runstall(CPUXtensaState *env); > -int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); > void xtensa_cpu_list(void); > void xtensa_sync_window_from_phys(CPUXtensaState *env); > void xtensa_sync_phys_from_window(CPUXtensaState *env); > -- > 2.25.1 > > <div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Sep 13, 2021 at 4:05 PM Richard Henderson <<a href="mailto:richard.henderson@linaro.org">richard.henderson@linaro.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">There is nothing target specific about this. The implementation<br> is host specific, but the declaration is 100% common.<br> <br> Reviewed-by: Alistair Francis <<a href="mailto:alistair.francis@wdc.com" target="_blank">alistair.francis@wdc.com</a>><br> Signed-off-by: Richard Henderson <<a href="mailto:richard.henderson@linaro.org" target="_blank">richard.henderson@linaro.org</a>><br> ---<br> include/exec/exec-all.h | 13 +++++++++++++<br> target/alpha/cpu.h | 6 ------<br> target/arm/cpu.h | 7 -------<br> target/avr/cpu.h | 2 --<br> target/cris/cpu.h | 8 --------<br> target/hexagon/cpu.h | 3 ---<br> target/hppa/cpu.h | 3 ---<br> target/i386/cpu.h | 7 -------<br> target/m68k/cpu.h | 8 --------<br> target/microblaze/cpu.h | 7 -------<br> target/mips/cpu.h | 3 ---<br> target/mips/internal.h | 2 --<br> target/nios2/cpu.h | 2 --<br> target/openrisc/cpu.h | 2 --<br> target/ppc/cpu.h | 7 -------<br> target/riscv/cpu.h | 2 --<br> target/rx/cpu.h | 4 ----<br> target/s390x/cpu.h | 7 -------<br> target/sh4/cpu.h | 3 ---<br> target/sparc/cpu.h | 2 --<br> target/tricore/cpu.h | 2 --<br> target/xtensa/cpu.h | 2 --<br> 22 files changed, 13 insertions(+), 89 deletions(-)<br></blockquote><div><br></div><div>Reviewed-By: Warner Losh <<a href="mailto:imp@bsdimp.com">imp@bsdimp.com</a>></div><div><br></div><div>Warner</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h<br> index 5d1b6d80fb..9d5987ba04 100644<br> --- a/include/exec/exec-all.h<br> +++ b/include/exec/exec-all.h<br> @@ -662,6 +662,19 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env,<br> }<br> return addr;<br> }<br> +<br> +/**<br> + * cpu_signal_handler<br> + * @signum: host signal number<br> + * @pinfo: host siginfo_t<br> + * @puc: host ucontext_t<br> + *<br> + * To be called from the SIGBUS and SIGSEGV signal handler to inform the<br> + * virtual cpu of exceptions. Returns true if the signal was handled by<br> + * the virtual CPU.<br> + */<br> +int cpu_signal_handler(int signum, void *pinfo, void *puc);<br> +<br> #else<br> static inline void mmap_lock(void) {}<br> static inline void mmap_unlock(void) {}<br> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h<br> index 4e993bd15b..ce9ec32199 100644<br> --- a/target/alpha/cpu.h<br> +++ b/target/alpha/cpu.h<br> @@ -287,7 +287,6 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,<br> int mmu_idx, uintptr_t retaddr);<br> <br> #define cpu_list alpha_cpu_list<br> -#define cpu_signal_handler cpu_alpha_signal_handler<br> <br> typedef CPUAlphaState CPUArchState;<br> typedef AlphaCPU ArchCPU;<br> @@ -440,11 +439,6 @@ void alpha_translate_init(void);<br> #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU<br> <br> void alpha_cpu_list(void);<br> -/* you can call this signal handler from your SIGBUS and SIGSEGV<br> - signal handlers to inform the virtual CPU of exceptions. non zero<br> - is returned if the signal was handled by the virtual CPU. */<br> -int cpu_alpha_signal_handler(int host_signum, void *pinfo,<br> - void *puc);<br> bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,<br> MMUAccessType access_type, int mmu_idx,<br> bool probe, uintptr_t retaddr);<br> diff --git a/target/arm/cpu.h b/target/arm/cpu.h<br> index cfd755cff9..6c78957e54 100644<br> --- a/target/arm/cpu.h<br> +++ b/target/arm/cpu.h<br> @@ -1121,12 +1121,6 @@ static inline bool is_a64(CPUARMState *env)<br> return env->aarch64;<br> }<br> <br> -/* you can call this signal handler from your SIGBUS and SIGSEGV<br> - signal handlers to inform the virtual CPU of exceptions. non zero<br> - is returned if the signal was handled by the virtual CPU. */<br> -int cpu_arm_signal_handler(int host_signum, void *pinfo,<br> - void *puc);<br> -<br> /**<br> * pmu_op_start/finish<br> * @env: CPUARMState<br> @@ -3015,7 +3009,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);<br> #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)<br> #define CPU_RESOLVING_TYPE TYPE_ARM_CPU<br> <br> -#define cpu_signal_handler cpu_arm_signal_handler<br> #define cpu_list arm_cpu_list<br> <br> /* ARM has the following "translation regimes" (as the ARM ARM calls them):<br> diff --git a/target/avr/cpu.h b/target/avr/cpu.h<br> index 93e3faa0a9..dceacf3cd7 100644<br> --- a/target/avr/cpu.h<br> +++ b/target/avr/cpu.h<br> @@ -175,7 +175,6 @@ static inline void set_avr_feature(CPUAVRState *env, int feature)<br> }<br> <br> #define cpu_list avr_cpu_list<br> -#define cpu_signal_handler cpu_avr_signal_handler<br> #define cpu_mmu_index avr_cpu_mmu_index<br> <br> static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch)<br> @@ -187,7 +186,6 @@ void avr_cpu_tcg_init(void);<br> <br> void avr_cpu_list(void);<br> int cpu_avr_exec(CPUState *cpu);<br> -int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc);<br> int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf,<br> int len, bool is_write);<br> <br> diff --git a/target/cris/cpu.h b/target/cris/cpu.h<br> index be021899ae..6603565f83 100644<br> --- a/target/cris/cpu.h<br> +++ b/target/cris/cpu.h<br> @@ -199,12 +199,6 @@ int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);<br> int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);<br> int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);<br> <br> -/* you can call this signal handler from your SIGBUS and SIGSEGV<br> - signal handlers to inform the virtual CPU of exceptions. non zero<br> - is returned if the signal was handled by the virtual CPU. */<br> -int cpu_cris_signal_handler(int host_signum, void *pinfo,<br> - void *puc);<br> -<br> void cris_initialize_tcg(void);<br> void cris_initialize_crisv10_tcg(void);<br> <br> @@ -250,8 +244,6 @@ enum {<br> #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)<br> #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU<br> <br> -#define cpu_signal_handler cpu_cris_signal_handler<br> -<br> /* MMU modes definitions */<br> #define MMU_USER_IDX 1<br> static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)<br> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h<br> index 2855dd3881..f7d043865b 100644<br> --- a/target/hexagon/cpu.h<br> +++ b/target/hexagon/cpu.h<br> @@ -129,9 +129,6 @@ typedef struct HexagonCPU {<br> <br> #include "cpu_bits.h"<br> <br> -#define cpu_signal_handler cpu_hexagon_signal_handler<br> -int cpu_hexagon_signal_handler(int host_signum, void *pinfo, void *puc);<br> -<br> static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc,<br> target_ulong *cs_base, uint32_t *flags)<br> {<br> diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h<br> index 7854675b90..d3cb7a279f 100644<br> --- a/target/hppa/cpu.h<br> +++ b/target/hppa/cpu.h<br> @@ -319,9 +319,6 @@ static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { }<br> void cpu_hppa_change_prot_id(CPUHPPAState *env);<br> #endif<br> <br> -#define cpu_signal_handler cpu_hppa_signal_handler<br> -<br> -int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc);<br> hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);<br> int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);<br> int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);<br> diff --git a/target/i386/cpu.h b/target/i386/cpu.h<br> index 7dd664791a..c2954c71ea 100644<br> --- a/target/i386/cpu.h<br> +++ b/target/i386/cpu.h<br> @@ -1947,12 +1947,6 @@ void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);<br> void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);<br> void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);<br> <br> -/* you can call this signal handler from your SIGBUS and SIGSEGV<br> - signal handlers to inform the virtual CPU of exceptions. non zero<br> - is returned if the signal was handled by the virtual CPU. */<br> -int cpu_x86_signal_handler(int host_signum, void *pinfo,<br> - void *puc);<br> -<br> /* cpu.c */<br> void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,<br> uint32_t vendor2, uint32_t vendor3);<br> @@ -2020,7 +2014,6 @@ uint64_t cpu_get_tsc(CPUX86State *env);<br> #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")<br> #endif<br> <br> -#define cpu_signal_handler cpu_x86_signal_handler<br> #define cpu_list x86_cpu_list<br> <br> /* MMU modes definitions */<br> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h<br> index 550eb028b6..a3423729ef 100644<br> --- a/target/m68k/cpu.h<br> +++ b/target/m68k/cpu.h<br> @@ -177,13 +177,6 @@ int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);<br> <br> void m68k_tcg_init(void);<br> void m68k_cpu_init_gdb(M68kCPU *cpu);<br> -/*<br> - * you can call this signal handler from your SIGBUS and SIGSEGV<br> - * signal handlers to inform the virtual CPU of exceptions. non zero<br> - * is returned if the signal was handled by the virtual CPU.<br> - */<br> -int cpu_m68k_signal_handler(int host_signum, void *pinfo,<br> - void *puc);<br> uint32_t cpu_m68k_get_ccr(CPUM68KState *env);<br> void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);<br> void cpu_m68k_set_sr(CPUM68KState *env, uint32_t);<br> @@ -563,7 +556,6 @@ enum {<br> #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX<br> #define CPU_RESOLVING_TYPE TYPE_M68K_CPU<br> <br> -#define cpu_signal_handler cpu_m68k_signal_handler<br> #define cpu_list m68k_cpu_list<br> <br> /* MMU modes definitions */<br> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h<br> index 40401c33b7..13ed3cd4dd 100644<br> --- a/target/microblaze/cpu.h<br> +++ b/target/microblaze/cpu.h<br> @@ -385,16 +385,9 @@ static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val)<br> }<br> <br> void mb_tcg_init(void);<br> -/* you can call this signal handler from your SIGBUS and SIGSEGV<br> - signal handlers to inform the virtual CPU of exceptions. non zero<br> - is returned if the signal was handled by the virtual CPU. */<br> -int cpu_mb_signal_handler(int host_signum, void *pinfo,<br> - void *puc);<br> <br> #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU<br> <br> -#define cpu_signal_handler cpu_mb_signal_handler<br> -<br> /* MMU modes definitions */<br> #define MMU_NOMMU_IDX 0<br> #define MMU_KERNEL_IDX 1<br> diff --git a/target/mips/cpu.h b/target/mips/cpu.h<br> index 1dfe69c6c0..56b1cbd091 100644<br> --- a/target/mips/cpu.h<br> +++ b/target/mips/cpu.h<br> @@ -1193,7 +1193,6 @@ struct MIPSCPU {<br> <br> void mips_cpu_list(void);<br> <br> -#define cpu_signal_handler cpu_mips_signal_handler<br> #define cpu_list mips_cpu_list<br> <br> extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);<br> @@ -1277,8 +1276,6 @@ enum {<br> */<br> #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0<br> <br> -int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);<br> -<br> #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU<br> #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX<br> #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU<br> diff --git a/target/mips/internal.h b/target/mips/internal.h<br> index eecdd10116..daddb05fd4 100644<br> --- a/target/mips/internal.h<br> +++ b/target/mips/internal.h<br> @@ -156,8 +156,6 @@ extern const VMStateDescription vmstate_mips_cpu;<br> <br> #endif /* !CONFIG_USER_ONLY */<br> <br> -#define cpu_signal_handler cpu_mips_signal_handler<br> -<br> static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)<br> {<br> return (env->CP0_Status & (1 << CP0St_IE)) &&<br> diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h<br> index 2ab82fdc71..88a511209c 100644<br> --- a/target/nios2/cpu.h<br> +++ b/target/nios2/cpu.h<br> @@ -193,7 +193,6 @@ struct Nios2CPU {<br> <br> void nios2_tcg_init(void);<br> void nios2_cpu_do_interrupt(CPUState *cs);<br> -int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc);<br> void dump_mmu(CPUNios2State *env);<br> void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags);<br> hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);<br> @@ -206,7 +205,6 @@ void do_nios2_semihosting(CPUNios2State *env);<br> #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU<br> <br> #define cpu_gen_code cpu_nios2_gen_code<br> -#define cpu_signal_handler cpu_nios2_signal_handler<br> <br> #define CPU_SAVE_VERSION 1<br> <br> diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h<br> index be6df81a81..187a4a114e 100644<br> --- a/target/openrisc/cpu.h<br> +++ b/target/openrisc/cpu.h<br> @@ -320,11 +320,9 @@ void openrisc_translate_init(void);<br> bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,<br> MMUAccessType access_type, int mmu_idx,<br> bool probe, uintptr_t retaddr);<br> -int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);<br> int print_insn_or1k(bfd_vma addr, disassemble_info *info);<br> <br> #define cpu_list cpu_openrisc_list<br> -#define cpu_signal_handler cpu_openrisc_signal_handler<br> <br> #ifndef CONFIG_USER_ONLY<br> extern const VMStateDescription vmstate_openrisc_cpu;<br> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h<br> index 362e7c4c5c..01d3773bc7 100644<br> --- a/target/ppc/cpu.h<br> +++ b/target/ppc/cpu.h<br> @@ -1278,12 +1278,6 @@ extern const VMStateDescription vmstate_ppc_cpu;<br> <br> /*****************************************************************************/<br> void ppc_translate_init(void);<br> -/*<br> - * you can call this signal handler from your SIGBUS and SIGSEGV<br> - * signal handlers to inform the virtual CPU of exceptions. non zero<br> - * is returned if the signal was handled by the virtual CPU.<br> - */<br> -int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc);<br> bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,<br> MMUAccessType access_type, int mmu_idx,<br> bool probe, uintptr_t retaddr);<br> @@ -1371,7 +1365,6 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);<br> #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX<br> #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU<br> <br> -#define cpu_signal_handler cpu_ppc_signal_handler<br> #define cpu_list ppc_cpu_list<br> <br> /* MMU modes definitions */<br> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h<br> index e735e53e26..465142616a 100644<br> --- a/target/riscv/cpu.h<br> +++ b/target/riscv/cpu.h<br> @@ -356,7 +356,6 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,<br> char *riscv_isa_string(RISCVCPU *cpu);<br> void riscv_cpu_list(void);<br> <br> -#define cpu_signal_handler riscv_cpu_signal_handler<br> #define cpu_list riscv_cpu_list<br> #define cpu_mmu_index riscv_cpu_mmu_index<br> <br> @@ -372,7 +371,6 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),<br> void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);<br> <br> void riscv_translate_init(void);<br> -int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);<br> void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,<br> uint32_t exception, uintptr_t pc);<br> <br> diff --git a/target/rx/cpu.h b/target/rx/cpu.h<br> index faa3606f52..4ac71aec37 100644<br> --- a/target/rx/cpu.h<br> +++ b/target/rx/cpu.h<br> @@ -134,13 +134,9 @@ int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);<br> hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);<br> <br> void rx_translate_init(void);<br> -int cpu_rx_signal_handler(int host_signum, void *pinfo,<br> - void *puc);<br> -<br> void rx_cpu_list(void);<br> void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);<br> <br> -#define cpu_signal_handler cpu_rx_signal_handler<br> #define cpu_list rx_cpu_list<br> <br> #include "exec/cpu-all.h"<br> diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h<br> index b26ae8fff2..3153d053e9 100644<br> --- a/target/s390x/cpu.h<br> +++ b/target/s390x/cpu.h<br> @@ -809,13 +809,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,<br> #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)<br> #define CPU_RESOLVING_TYPE TYPE_S390_CPU<br> <br> -/* you can call this signal handler from your SIGBUS and SIGSEGV<br> - signal handlers to inform the virtual CPU of exceptions. non zero<br> - is returned if the signal was handled by the virtual CPU. */<br> -int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc);<br> -#define cpu_signal_handler cpu_s390x_signal_handler<br> -<br> -<br> /* interrupt.c */<br> #define RA_IGNORED 0<br> void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra);<br> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h<br> index 017a770214..56f7c32df9 100644<br> --- a/target/sh4/cpu.h<br> +++ b/target/sh4/cpu.h<br> @@ -213,8 +213,6 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,<br> int mmu_idx, uintptr_t retaddr);<br> <br> void sh4_translate_init(void);<br> -int cpu_sh4_signal_handler(int host_signum, void *pinfo,<br> - void *puc);<br> bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,<br> MMUAccessType access_type, int mmu_idx,<br> bool probe, uintptr_t retaddr);<br> @@ -250,7 +248,6 @@ void cpu_load_tlb(CPUSH4State * env);<br> #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX<br> #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU<br> <br> -#define cpu_signal_handler cpu_sh4_signal_handler<br> #define cpu_list sh4_cpu_list<br> <br> /* MMU modes definitions */<br> diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h<br> index ff8ae73002..6b40d02237 100644<br> --- a/target/sparc/cpu.h<br> +++ b/target/sparc/cpu.h<br> @@ -649,13 +649,11 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,<br> int mmu_idx);<br> #endif<br> #endif<br> -int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);<br> <br> #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU<br> #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX<br> #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU<br> <br> -#define cpu_signal_handler cpu_sparc_signal_handler<br> #define cpu_list sparc_cpu_list<br> <br> /* MMU modes definitions */<br> diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h<br> index 4b61a2c03f..c461387e71 100644<br> --- a/target/tricore/cpu.h<br> +++ b/target/tricore/cpu.h<br> @@ -362,7 +362,6 @@ void fpu_set_state(CPUTriCoreState *env);<br> <br> void tricore_cpu_list(void);<br> <br> -#define cpu_signal_handler cpu_tricore_signal_handler<br> #define cpu_list tricore_cpu_list<br> <br> static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)<br> @@ -377,7 +376,6 @@ typedef TriCoreCPU ArchCPU;<br> <br> void cpu_state_reset(CPUTriCoreState *s);<br> void tricore_tcg_init(void);<br> -int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc);<br> <br> static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc,<br> target_ulong *cs_base, uint32_t *flags)<br> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h<br> index cbb720e7cc..646965f379 100644<br> --- a/target/xtensa/cpu.h<br> +++ b/target/xtensa/cpu.h<br> @@ -584,7 +584,6 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,<br> MMUAccessType access_type,<br> int mmu_idx, uintptr_t retaddr);<br> <br> -#define cpu_signal_handler cpu_xtensa_signal_handler<br> #define cpu_list xtensa_cpu_list<br> <br> #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU<br> @@ -613,7 +612,6 @@ void check_interrupts(CPUXtensaState *s);<br> void xtensa_irq_init(CPUXtensaState *env);<br> qemu_irq *xtensa_get_extints(CPUXtensaState *env);<br> qemu_irq xtensa_get_runstall(CPUXtensaState *env);<br> -int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);<br> void xtensa_cpu_list(void);<br> void xtensa_sync_window_from_phys(CPUXtensaState *env);<br> void xtensa_sync_phys_from_window(CPUXtensaState *env);<br> -- <br> 2.25.1<br> <br> </blockquote></div></div>
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5d1b6d80fb..9d5987ba04 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -662,6 +662,19 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, } return addr; } + +/** + * cpu_signal_handler + * @signum: host signal number + * @pinfo: host siginfo_t + * @puc: host ucontext_t + * + * To be called from the SIGBUS and SIGSEGV signal handler to inform the + * virtual cpu of exceptions. Returns true if the signal was handled by + * the virtual CPU. + */ +int cpu_signal_handler(int signum, void *pinfo, void *puc); + #else static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 4e993bd15b..ce9ec32199 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -287,7 +287,6 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, int mmu_idx, uintptr_t retaddr); #define cpu_list alpha_cpu_list -#define cpu_signal_handler cpu_alpha_signal_handler typedef CPUAlphaState CPUArchState; typedef AlphaCPU ArchCPU; @@ -440,11 +439,6 @@ void alpha_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU void alpha_cpu_list(void); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_alpha_signal_handler(int host_signum, void *pinfo, - void *puc); bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cfd755cff9..6c78957e54 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1121,12 +1121,6 @@ static inline bool is_a64(CPUARMState *env) return env->aarch64; } -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_arm_signal_handler(int host_signum, void *pinfo, - void *puc); - /** * pmu_op_start/finish * @env: CPUARMState @@ -3015,7 +3009,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU -#define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list /* ARM has the following "translation regimes" (as the ARM ARM calls them): diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 93e3faa0a9..dceacf3cd7 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -175,7 +175,6 @@ static inline void set_avr_feature(CPUAVRState *env, int feature) } #define cpu_list avr_cpu_list -#define cpu_signal_handler cpu_avr_signal_handler #define cpu_mmu_index avr_cpu_mmu_index static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) @@ -187,7 +186,6 @@ void avr_cpu_tcg_init(void); void avr_cpu_list(void); int cpu_avr_exec(CPUState *cpu); -int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc); int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, int len, bool is_write); diff --git a/target/cris/cpu.h b/target/cris/cpu.h index be021899ae..6603565f83 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -199,12 +199,6 @@ int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_cris_signal_handler(int host_signum, void *pinfo, - void *puc); - void cris_initialize_tcg(void); void cris_initialize_crisv10_tcg(void); @@ -250,8 +244,6 @@ enum { #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU -#define cpu_signal_handler cpu_cris_signal_handler - /* MMU modes definitions */ #define MMU_USER_IDX 1 static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 2855dd3881..f7d043865b 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -129,9 +129,6 @@ typedef struct HexagonCPU { #include "cpu_bits.h" -#define cpu_signal_handler cpu_hexagon_signal_handler -int cpu_hexagon_signal_handler(int host_signum, void *pinfo, void *puc); - static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7854675b90..d3cb7a279f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -319,9 +319,6 @@ static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } void cpu_hppa_change_prot_id(CPUHPPAState *env); #endif -#define cpu_signal_handler cpu_hppa_signal_handler - -int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7dd664791a..c2954c71ea 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1947,12 +1947,6 @@ void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_x86_signal_handler(int host_signum, void *pinfo, - void *puc); - /* cpu.c */ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, uint32_t vendor2, uint32_t vendor3); @@ -2020,7 +2014,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") #endif -#define cpu_signal_handler cpu_x86_signal_handler #define cpu_list x86_cpu_list /* MMU modes definitions */ diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 550eb028b6..a3423729ef 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -177,13 +177,6 @@ int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void m68k_tcg_init(void); void m68k_cpu_init_gdb(M68kCPU *cpu); -/* - * you can call this signal handler from your SIGBUS and SIGSEGV - * signal handlers to inform the virtual CPU of exceptions. non zero - * is returned if the signal was handled by the virtual CPU. - */ -int cpu_m68k_signal_handler(int host_signum, void *pinfo, - void *puc); uint32_t cpu_m68k_get_ccr(CPUM68KState *env); void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); @@ -563,7 +556,6 @@ enum { #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_M68K_CPU -#define cpu_signal_handler cpu_m68k_signal_handler #define cpu_list m68k_cpu_list /* MMU modes definitions */ diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 40401c33b7..13ed3cd4dd 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -385,16 +385,9 @@ static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val) } void mb_tcg_init(void); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_mb_signal_handler(int host_signum, void *pinfo, - void *puc); #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU -#define cpu_signal_handler cpu_mb_signal_handler - /* MMU modes definitions */ #define MMU_NOMMU_IDX 0 #define MMU_KERNEL_IDX 1 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1dfe69c6c0..56b1cbd091 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1193,7 +1193,6 @@ struct MIPSCPU { void mips_cpu_list(void); -#define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); @@ -1277,8 +1276,6 @@ enum { */ #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 -int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); - #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU diff --git a/target/mips/internal.h b/target/mips/internal.h index eecdd10116..daddb05fd4 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -156,8 +156,6 @@ extern const VMStateDescription vmstate_mips_cpu; #endif /* !CONFIG_USER_ONLY */ -#define cpu_signal_handler cpu_mips_signal_handler - static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2ab82fdc71..88a511209c 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -193,7 +193,6 @@ struct Nios2CPU { void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); -int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc); void dump_mmu(CPUNios2State *env); void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); @@ -206,7 +205,6 @@ void do_nios2_semihosting(CPUNios2State *env); #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU #define cpu_gen_code cpu_nios2_gen_code -#define cpu_signal_handler cpu_nios2_signal_handler #define CPU_SAVE_VERSION 1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index be6df81a81..187a4a114e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -320,11 +320,9 @@ void openrisc_translate_init(void); bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); int print_insn_or1k(bfd_vma addr, disassemble_info *info); #define cpu_list cpu_openrisc_list -#define cpu_signal_handler cpu_openrisc_signal_handler #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_openrisc_cpu; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 362e7c4c5c..01d3773bc7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1278,12 +1278,6 @@ extern const VMStateDescription vmstate_ppc_cpu; /*****************************************************************************/ void ppc_translate_init(void); -/* - * you can call this signal handler from your SIGBUS and SIGSEGV - * signal handlers to inform the virtual CPU of exceptions. non zero - * is returned if the signal was handled by the virtual CPU. - */ -int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc); bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -1371,7 +1365,6 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val); #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU -#define cpu_signal_handler cpu_ppc_signal_handler #define cpu_list ppc_cpu_list /* MMU modes definitions */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e735e53e26..465142616a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -356,7 +356,6 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); -#define cpu_signal_handler riscv_cpu_signal_handler #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index @@ -372,7 +371,6 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); void riscv_translate_init(void); -int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc); diff --git a/target/rx/cpu.h b/target/rx/cpu.h index faa3606f52..4ac71aec37 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -134,13 +134,9 @@ int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void rx_translate_init(void); -int cpu_rx_signal_handler(int host_signum, void *pinfo, - void *puc); - void rx_cpu_list(void); void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); -#define cpu_signal_handler cpu_rx_signal_handler #define cpu_list rx_cpu_list #include "exec/cpu-all.h" diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index b26ae8fff2..3153d053e9 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -809,13 +809,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_S390_CPU -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ -int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); -#define cpu_signal_handler cpu_s390x_signal_handler - - /* interrupt.c */ #define RA_IGNORED 0 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra); diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 017a770214..56f7c32df9 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -213,8 +213,6 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, int mmu_idx, uintptr_t retaddr); void sh4_translate_init(void); -int cpu_sh4_signal_handler(int host_signum, void *pinfo, - void *puc); bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -250,7 +248,6 @@ void cpu_load_tlb(CPUSH4State * env); #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU -#define cpu_signal_handler cpu_sh4_signal_handler #define cpu_list sh4_cpu_list /* MMU modes definitions */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index ff8ae73002..6b40d02237 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -649,13 +649,11 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, int mmu_idx); #endif #endif -int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU -#define cpu_signal_handler cpu_sparc_signal_handler #define cpu_list sparc_cpu_list /* MMU modes definitions */ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 4b61a2c03f..c461387e71 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -362,7 +362,6 @@ void fpu_set_state(CPUTriCoreState *env); void tricore_cpu_list(void); -#define cpu_signal_handler cpu_tricore_signal_handler #define cpu_list tricore_cpu_list static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) @@ -377,7 +376,6 @@ typedef TriCoreCPU ArchCPU; void cpu_state_reset(CPUTriCoreState *s); void tricore_tcg_init(void); -int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc); static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index cbb720e7cc..646965f379 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -584,7 +584,6 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); -#define cpu_signal_handler cpu_xtensa_signal_handler #define cpu_list xtensa_cpu_list #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU @@ -613,7 +612,6 @@ void check_interrupts(CPUXtensaState *s); void xtensa_irq_init(CPUXtensaState *env); qemu_irq *xtensa_get_extints(CPUXtensaState *env); qemu_irq xtensa_get_runstall(CPUXtensaState *env); -int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); void xtensa_cpu_list(void); void xtensa_sync_window_from_phys(CPUXtensaState *env); void xtensa_sync_phys_from_window(CPUXtensaState *env);