| Message ID | 20210823195529.560295-14-richard.henderson@linaro.org |
|---|---|
| State | Accepted |
| Commit | 23c108868943f9315be0bb675f6cd4dac7295b99 |
| Headers | show |
| Series | target/riscv: Use tcg_constant_* | expand |
On Tue, Aug 24, 2021 at 4:05 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > These operations can be done in one instruction on some hosts. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/riscv/insn_trans/trans_rvi.c.inc | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On Tue, Aug 24, 2021 at 6:05 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > These operations can be done in one instruction on some hosts. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_rvi.c.inc | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc > index e4726e618c..9e8d99be51 100644 > --- a/target/riscv/insn_trans/trans_rvi.c.inc > +++ b/target/riscv/insn_trans/trans_rvi.c.inc > @@ -347,18 +347,28 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a) > return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); > } > > +static void gen_srliw(TCGv dst, TCGv src, target_long shamt) > +{ > + tcg_gen_extract_tl(dst, src, shamt, 32 - shamt); > +} > + > static bool trans_srliw(DisasContext *ctx, arg_srliw *a) > { > REQUIRE_64BIT(ctx); > ctx->w = true; > - return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl); > + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw); > +} > + > +static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) > +{ > + tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt); > } > > static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) > { > REQUIRE_64BIT(ctx); > ctx->w = true; > - return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl); > + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw); > } > > static bool trans_addw(DisasContext *ctx, arg_addw *a) > -- > 2.25.1 > >
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index e4726e618c..9e8d99be51 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -347,18 +347,28 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a) return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl); } +static void gen_srliw(TCGv dst, TCGv src, target_long shamt) +{ + tcg_gen_extract_tl(dst, src, shamt, 32 - shamt); +} + static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { REQUIRE_64BIT(ctx); ctx->w = true; - return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl); + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw); +} + +static void gen_sraiw(TCGv dst, TCGv src, target_long shamt) +{ + tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt); } static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { REQUIRE_64BIT(ctx); ctx->w = true; - return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl); + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw); } static bool trans_addw(DisasContext *ctx, arg_addw *a)
These operations can be done in one instruction on some hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/insn_trans/trans_rvi.c.inc | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) -- 2.25.1