[v2,13/21] target/riscv: Use get_gpr in branches

Message ID	20210817211803.283639-14-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH v2 13/21] target/riscv: Use get_gpr in branches Date: Tue, 17 Aug 2021 11:17:55 -1000 Message-Id: <20210817211803.283639-14-richard.henderson@linaro.org> In-Reply-To: <20210817211803.283639-1-richard.henderson@linaro.org> References: <20210817211803.283639-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Cc: Alistair.Francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/riscv: Use tcg_constant_* \| expand [v2,00/21] target/riscv: Use tcg_constant_* [v2,01/21] target/riscv: Use tcg_constant_* [v2,02/21] target/riscv: Clean up division helpers [v2,03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr [v2,04/21] target/riscv: Introduce DisasExtend and new helpers [v2,05/21] target/riscv: Add DisasExtend to gen_arith* [v2,06/21] target/riscv: Remove gen_arith_div* [v2,07/21] target/riscv: Use gen_arith for mulh and mulhu [v2,08/21] target/riscv: Move gen_* helpers for RVM [v2,09/21] target/riscv: Move gen_* helpers for RVB [v2,10/21] target/riscv: Add DisasExtend to gen_unary [v2,11/21] target/riscv: Use DisasExtend in shift operations [v2,12/21] target/riscv: Add gen_greviw [v2,13/21] target/riscv: Use get_gpr in branches [v2,14/21] target/riscv: Use {get, dest}_gpr for integer load/store [v2,15/21] target/riscv: Reorg csr instructions [v2,16/21] target/riscv: Use {get,dest}_gpr for RVA [v2,17/21] target/riscv: Use gen_shift_imm_fn for slli_uw [v2,18/21] target/riscv: Use {get,dest}_gpr for RVF [v2,19/21] target/riscv: Use {get,dest}_gpr for RVD [v2,20/21] target/riscv: Tidy trans_rvh.c.inc [v2,21/21] target/riscv: Use {get,dest}_gpr for RVV

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20210817211803.283639-14-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v2 13/21] target/riscv: Use get_gpr in branches
Date: Tue, 17 Aug 2021 11:17:55 -1000
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Series

target/riscv: Use tcg_constant_* | expand

Narrow the scope of t0 in trans_jalr. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/insn_trans/trans_rvi.c.inc | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) -- 2.25.1

Comments

Bin Meng Aug. 19, 2021, 6:19 a.m. UTC | #1

On Wed, Aug 18, 2021 at 5:26 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Narrow the scope of t0 in trans_jalr.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/riscv/insn_trans/trans_rvi.c.inc | 25 ++++++++++---------------

>  1 file changed, 10 insertions(+), 15 deletions(-)

>


Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index e25f64c45a..af3e0bc0e6 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -54,24 +54,25 @@  static bool trans_jal(DisasContext *ctx, arg_jal *a)
 
 static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
 {
-    /* no chaining with JALR */
     TCGLabel *misaligned = NULL;
-    TCGv t0 = tcg_temp_new();
 
-
-    gen_get_gpr(ctx, cpu_pc, a->rs1);
-    tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+    tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
     tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
 
     if (!has_ext(ctx, RVC)) {
+        TCGv t0 = tcg_temp_new();
+
         misaligned = gen_new_label();
         tcg_gen_andi_tl(t0, cpu_pc, 0x2);
         tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+        tcg_temp_free(t0);
     }
 
     if (a->rd != 0) {
         tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
     }
+
+    /* No chaining with JALR. */
     lookup_and_goto_ptr(ctx);
 
     if (misaligned) {
@@ -80,21 +81,18 @@  static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
     }
     ctx->base.is_jmp = DISAS_NORETURN;
 
-    tcg_temp_free(t0);
     return true;
 }
 
 static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
 {
     TCGLabel *l = gen_new_label();
-    TCGv source1, source2;
-    source1 = tcg_temp_new();
-    source2 = tcg_temp_new();
-    gen_get_gpr(ctx, source1, a->rs1);
-    gen_get_gpr(ctx, source2, a->rs2);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
 
-    tcg_gen_brcond_tl(cond, source1, source2, l);
+    tcg_gen_brcond_tl(cond, src1, src2, l);
     gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+
     gen_set_label(l); /* branch taken */
 
     if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
@@ -105,9 +103,6 @@  static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
     }
     ctx->base.is_jmp = DISAS_NORETURN;
 
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
-
     return true;
 }

[v2,13/21] target/riscv: Use get_gpr in branches

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