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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id c23sm13718532pfn.140.2021.08.02.21.15.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Aug 2021 21:15:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 18/55] target/sparc: Implement do_unaligned_access for user-only Date: Mon, 2 Aug 2021 18:14:06 -1000 Message-Id: <20210803041443.55452-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210803041443.55452-1-richard.henderson@linaro.org> References: <20210803041443.55452-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Mark Cave-Ayland Signed-off-by: Richard Henderson --- linux-user/sparc/cpu_loop.c | 11 +++++++++++ target/sparc/cpu.c | 2 +- target/sparc/mmu_helper.c | 4 +++- 3 files changed, 15 insertions(+), 2 deletions(-) -- 2.25.1 Acked-by: Mark Cave-Ayland diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index 02532f198d..612e77807e 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -272,6 +272,17 @@ void cpu_loop (CPUSPARCState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); } break; + case TT_UNALIGNED: + info.si_signo = TARGET_SIGBUS; + info.si_errno = 0; + info.si_code = TARGET_BUS_ADRALN; +#ifdef TARGET_SPARC64 + info._sifields._sigfault._addr = env->dmmu.sfar; +#else + info._sifields._sigfault._addr = env->mmuregs[4]; +#endif + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; case EXCP_DEBUG: info.si_signo = TARGET_SIGTRAP; info.si_errno = 0; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index da6b30ec74..d33d41e837 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -865,11 +865,11 @@ static const struct TCGCPUOps sparc_tcg_ops = { .synchronize_from_tb = sparc_cpu_synchronize_from_tb, .cpu_exec_interrupt = sparc_cpu_exec_interrupt, .tlb_fill = sparc_cpu_tlb_fill, + .do_unaligned_access = sparc_cpu_do_unaligned_access, #ifndef CONFIG_USER_ONLY .do_interrupt = sparc_cpu_do_interrupt, .do_transaction_failed = sparc_cpu_do_transaction_failed, - .do_unaligned_access = sparc_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 2f260b0085..6b4aa32181 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -946,6 +946,7 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } return phys_addr; } +#endif /* CONFIG_USER_ONLY */ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, @@ -956,7 +957,9 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, CPUSPARCState *env = &cpu->env; #ifdef TARGET_SPARC64 +#ifndef CONFIG_USER_ONLY env->dmmu.sfsr = build_sfsr(env, mmu_idx, access_type); +#endif env->dmmu.sfar = addr; #else env->mmuregs[4] = addr; @@ -964,4 +967,3 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } -#endif /* CONFIG_USER_ONLY */