From patchwork Tue Aug 3 04:13:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 490848 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:396:0:0:0:0 with SMTP id y22csp308261jap; Mon, 2 Aug 2021 21:21:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyV3mI6TtKFYycoIKDLcTx1HFi9SGmyT4jkmCnc/MtxWPalteLEUOqlwltBA7Z1px1wPH55 X-Received: by 2002:a25:2b48:: with SMTP id r69mr5178609ybr.448.1627964474112; Mon, 02 Aug 2021 21:21:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627964474; cv=none; d=google.com; s=arc-20160816; b=Uz73xUi7VoIyU5tB3YG4YqfblPebxWgDrIO4e3Zpn30YtH7IRPSkGjD2IFwsWqJFZa PJHR1YJvihNmObVZq6+ow7qD694uLKMQ4xaOUNN0zrMlHKf8XsKgcZfcCEy2yuHc/4KD DFWvRmxegrFuuNzE/ufDvL+P03Obrypb8lVQnkmZ30+5cPC4gFnFfPxL6gts5knSbmG8 d8W2uRzYDd7hGSQRmPdP2ZroFZ+IKRf2/4gy4k0QkzyIp9KdzzSbWNh3IZ+y57JjKFcf drhfc97GaWO9X4V4+zVNoX4HeaX06ZTBP9a/NSkTw681Wzdx7p6ovxvbLcnqWcoNVSNn 94Yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sDqHuydfvja3hUkz7uNegNZUjAODAQ28Kwe+4YIPszs=; b=Uvk8ch0DP2sdwMkhPxQqow3W6cPMGHlFE3gULXXD/HpZPYIzXBIUJqIxnPS5ZB5pNt djZtae2OjZ0Y1jbzv9t/V4RjibX181cwkQaRSp1uuy7W7P+O/BZQzp/bI9io4pmqYyg8 yDC2tXD4CAx7RSLEG/kSTFAlpMALzw/FwYxFfyMyd7lfqXJlGTY4M9OEc9vJkp/AQSST K8kRJdxT4aJHAS56u4LTl8sxPUzdAW2u9iIVx5v7jwrOW6Ywu2QeHIv8oCVfO3zhJlTw gDuSs7KaFjJEiOUV6rdzoZhUQCOv2yfNoW5KfrY8C3x0EDg5FK1r6DXX+78gOfvyny4o 5Cvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fJ1uwkzb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j4si13923837ybl.127.2021.08.02.21.21.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 02 Aug 2021 21:21:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fJ1uwkzb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42406 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mAlvV-0003lC-Gc for patch@linaro.org; Tue, 03 Aug 2021 00:21:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56610) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mAlpV-0002st-QJ for qemu-devel@nongnu.org; Tue, 03 Aug 2021 00:15:01 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:40539) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mAlpT-00027y-Rq for qemu-devel@nongnu.org; Tue, 03 Aug 2021 00:15:01 -0400 Received: by mail-pl1-x62b.google.com with SMTP id c16so22133160plh.7 for ; Mon, 02 Aug 2021 21:14:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sDqHuydfvja3hUkz7uNegNZUjAODAQ28Kwe+4YIPszs=; b=fJ1uwkzbfCtHO4ZhobT+1nmlzDafpZNjUPwd70YbEjIPzHw2faFlI0vj7TFWbkcAjO R6Jcq2Tg0oZTZl4bWOZO9+LpfJYhGWAjxoMn1RPHTmheLfqdpgvh96h++NjsEyTZywTo KaSPwilaj79YAtEm1hfyPPEYrpEEZTxupy3qVLA9tUytNZA9gnWL903/zUdVRMgXx1YD tQrgM4jFSX6hpqz5gdtrrvGW0fC5VzTTktpcbTkOQbAEnoYFBF9+cqksHHD06xh+whyK TJbbW4rQLTBOHzm98JTCEvP0MsCfapxeWto0laE0vjTfzpaIC9AmTy2yzIBoL383CjG2 5zog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sDqHuydfvja3hUkz7uNegNZUjAODAQ28Kwe+4YIPszs=; b=BZAe6UwCroI0KNYHbKP3/AT73DA+jjGpPskWqbB1rvLFnpe1Iu0tppDd8g45uSkXVH BTHXH129TEE9srLP5g1qG7OolezG7noLS7zwqMV1QrOPyf8z3OD2JZR+DLZN25aoCcRL s6sGP/qUmdE17rcIra7WK7225TKtfTWrtUJdaPe1YD4YYVk7enW4wb1Du2WXiN9R6OfN /wu19iw3GR8YUMiXNluM9+zNSuoUrmEAWOivYwyVfL6FVFlzyj/gnLZPAE19xSj3GUX4 fOLDbOc2ZdfwtChcTGhov2r1jy2cVj2NPXR1dGd+jtlnD0+cWgddK2G7UKcWu4bPSJBl Uw+g== X-Gm-Message-State: AOAM533S/S3B3ZOutnd04UmIu1OuhFWtK8dbV3VXRagniXDQNlnc2I0P 9DLAEEa4+j72MB4C03X4IbwRjQu5DMPp3A== X-Received: by 2002:a65:680d:: with SMTP id l13mr1419169pgt.307.1627964098753; Mon, 02 Aug 2021 21:14:58 -0700 (PDT) Received: from localhost.localdomain (rrcs-173-198-77-218.west.biz.rr.com. [173.198.77.218]) by smtp.gmail.com with ESMTPSA id c23sm13718532pfn.140.2021.08.02.21.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Aug 2021 21:14:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 11/55] target/riscv: Implement do_unaligned_access for user-only Date: Mon, 2 Aug 2021 18:13:59 -1000 Message-Id: <20210803041443.55452-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210803041443.55452-1-richard.henderson@linaro.org> References: <20210803041443.55452-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 7 +++++++ target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 8 +++++++- 3 files changed, 15 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 74a9628dc9..0428140d86 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -92,6 +92,13 @@ void cpu_loop(CPURISCVState *env) sigcode = TARGET_SEGV_MAPERR; sigaddr = env->badaddr; break; + case RISCV_EXCP_INST_ADDR_MIS: + case RISCV_EXCP_LOAD_ADDR_MIS: + case RISCV_EXCP_STORE_AMO_ADDR_MIS: + signum = TARGET_SIGBUS; + sigcode = TARGET_BUS_ADRALN; + sigaddr = env->badaddr; + break; case RISCV_EXCP_SEMIHOST: env->gpr[xA0] = do_common_semihosting(cs); env->pc += 4; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 991a6bb760..591d17e62d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -644,11 +644,11 @@ static const struct TCGCPUOps riscv_tcg_ops = { .synchronize_from_tb = riscv_cpu_synchronize_from_tb, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .tlb_fill = riscv_cpu_tlb_fill, + .do_unaligned_access = riscv_cpu_do_unaligned_access, #ifndef CONFIG_USER_ONLY .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, - .do_unaligned_access = riscv_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 968cb8046f..a440b2834f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -727,6 +727,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); } +#endif /* !CONFIG_USER_ONLY */ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, @@ -734,6 +735,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; + switch (access_type) { case MMU_INST_FETCH: cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; @@ -748,11 +750,15 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, g_assert_not_reached(); } env->badaddr = addr; + +#ifdef CONFIG_USER_ONLY + cpu_loop_exit_restore(cs, retaddr); +#else env->two_stage_lookup = riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(env, cs->exception_index, retaddr); +#endif } -#endif /* !CONFIG_USER_ONLY */ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx,