[for-6.2,29/43] target/ppc: Use MO_128 for 16 byte atomics

Message ID	20210729004647.282017-30-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH for-6.2 29/43] target/ppc: Use MO_128 for 16 byte atomics Date: Wed, 28 Jul 2021 14:46:33 -1000 Message-Id: <20210729004647.282017-30-richard.henderson@linaro.org> In-Reply-To: <20210729004647.282017-1-richard.henderson@linaro.org> References: <20210729004647.282017-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Cc: qemu-ppc@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	Unaligned accesses for user-only \| expand [for-6.2,00/43] Unaligned accesses for user-only [for-6.2,01/43] hw/core: Make do_unaligned_access available to user-only [for-6.2,02/43] target/alpha: Implement do_unaligned_access for user-only [for-6.2,03/43] target/arm: Implement do_unaligned_access for user-only [for-6.2,04/43] target/hppa: Implement do_unaligned_access for user-only [for-6.2,05/43] target/microblaze: Implement do_unaligned_access for user-only [for-6.2,06/43] target/mips: Implement do_unaligned_access for user-only [for-6.2,07/43] target/ppc: Set fault address in ppc_cpu_do_unaligned_access [for-6.2,08/43] target/ppc: Implement do_unaligned_access for user-only [for-6.2,09/43] target/riscv: Implement do_unaligned_access for user-only [for-6.2,10/43] target/s390x: Implement do_unaligned_access for user-only [for-6.2,11/43] target/sh4: Set fault address in superh_cpu_do_unaligned_access [for-6.2,12/43] target/sh4: Implement do_unaligned_access for user-only [for-6.2,13/43] target/sparc: Remove DEBUG_UNALIGNED [for-6.2,14/43] target/sparc: Set fault address in sparc_cpu_do_unaligned_access [for-6.2,15/43] target/sparc: Implement do_unaligned_access for user-only [for-6.2,16/43] target/xtensa: Implement do_unaligned_access for user-only [for-6.2,17/43] accel/tcg: Report unaligned atomics for user-only [for-6.2,18/43] accel/tcg: Drop signness in tracing in cputlb.c [for-6.2,19/43] tcg: Expand MO_SIZE to 3 bits [for-6.2,20/43] tcg: Rename TCGMemOpIdx to MemOpIdx [for-6.2,21/43] tcg: Split out MemOpIdx to exec/memopidx.h [for-6.2,22/43] trace/mem: Pass MemOpIdx to trace_mem_get_info [for-6.2,23/43] accel/tcg: Remove double bswap for helper_atomic_sto__mmu [for-6.2,24/43] accel/tcg: Pass MemOpIdx to atomic_trace__post [for-6.2,25/43] plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb [for-6.2,26/43] trace: Split guest_mem_before [for-6.2,27/43] target/arm: Use MO_128 for 16 byte atomics [for-6.2,28/43] target/i386: Use MO_128 for 16 byte atomics [for-6.2,29/43] target/ppc: Use MO_128 for 16 byte atomics [for-6.2,30/43] target/s390x: Use MO_128 for 16 byte atomics [for-6.2,31/43] target/hexagon: Implement cpu_mmu_index [for-6.2,32/43] accel/tcg: Add cpu_{ld,st}_mmu interfaces [for-6.2,33/43] accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h [for-6.2,34/43] target/mips: Use cpu__data_ra for msa load/store [for-6.2,35/43] target/mips: Use 8-byte memory ops for msa load/store [for-6.2,36/43] target/s390x: Use cpu__mmu instead of helper__mmu [for-6.2,37/43] target/sparc: Use cpu__mmu instead of helper__mmu [for-6.2,38/43] target/arm: Use cpu__mmu instead of helper__mmu [for-6.2,39/43] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h [for-6.2,40/43] linux-user/alpha: Remove TARGET_ALIGNED_ONLY [for-6.2,41/43] tcg: Add helper_unaligned_mmu for user-only sigbus [for-6.2,42/43] tcg/i386: Support raising sigbus for user-only [for-6.2,43/43] tests/tcg/multiarch: Add sigbus.c

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20210729004647.282017-30-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH for-6.2 29/43] target/ppc: Use MO_128 for 16 byte atomics
Date: Wed, 28 Jul 2021 14:46:33 -1000
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Series

Unaligned accesses for user-only | expand

Comments

Philippe Mathieu-Daudé July 29, 2021, 6:34 a.m. UTC | #1

On 7/29/21 2:46 AM, Richard Henderson wrote:
> Cc: qemu-ppc@nongnu.org

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/ppc/translate.c | 12 +++++++-----

>  1 file changed, 7 insertions(+), 5 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 171b216e17..540efa858f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3461,10 +3461,12 @@  static void gen_std(DisasContext *ctx)
             if (HAVE_ATOMIC128) {
                 TCGv_i32 oi = tcg_temp_new_i32();
                 if (ctx->le_mode) {
-                    tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
+                    tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128,
+                                                        ctx->mem_idx));
                     gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
                 } else {
-                    tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
+                    tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128,
+                                                        ctx->mem_idx));
                     gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
                 }
                 tcg_temp_free_i32(oi);
@@ -4066,11 +4068,11 @@  static void gen_lqarx(DisasContext *ctx)
         if (HAVE_ATOMIC128) {
             TCGv_i32 oi = tcg_temp_new_i32();
             if (ctx->le_mode) {
-                tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16,
+                tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN,
                                                     ctx->mem_idx));
                 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
             } else {
-                tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16,
+                tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN,
                                                     ctx->mem_idx));
                 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
             }
@@ -4121,7 +4123,7 @@  static void gen_stqcx_(DisasContext *ctx)
 
     if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
         if (HAVE_CMPXCHG128) {
-            TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);
+            TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN);
             if (ctx->le_mode) {
                 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,
                                              EA, lo, hi, oi);

[for-6.2,29/43] target/ppc: Use MO_128 for 16 byte atomics

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