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[2603:800c:3202:ffa7:dcaa:9e71:a2b2:2604]) by smtp.gmail.com with ESMTPSA id t205sm1305005pfc.32.2021.07.28.17.47.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 17:47:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.2 14/43] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Date: Wed, 28 Jul 2021 14:46:18 -1000 Message-Id: <20210729004647.282017-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210729004647.282017-1-richard.henderson@linaro.org> References: <20210729004647.282017-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We ought to have been recording the virtual address for reporting to the guest trap handler. Mirror the SFSR FIXME from the sparc64 version of get_physical_address_data. Cc: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.25.1 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 974afea041..7367b48c8b 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1963,6 +1963,14 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; +#ifdef TARGET_SPARC64 + /* FIXME: ASI field in SFSR must be set */ + env->dmmu.sfsr = SFSR_VALID_BIT; /* Fault status register */ + env->dmmu.sfar = addr; /* Fault address register */ +#else + env->mmuregs[4] = addr; +#endif + cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } #endif