From patchwork Thu Jul 29 00:46:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 488624 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:1185:0:0:0:0 with SMTP id f5csp1703858jas; Wed, 28 Jul 2021 17:55:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxlyVdasCNzHQBr5kRK8gz41X2NNylsI8MWiL/ihuKKjrYBMjnDbS9KX1hh71JbVRWEP/kl X-Received: by 2002:a05:620a:70a:: with SMTP id 10mr2626206qkc.177.1627520127336; Wed, 28 Jul 2021 17:55:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627520127; cv=none; d=google.com; s=arc-20160816; b=mxGZLHC6bG3GmLuDzrcyar+hNp9ToISmJjQM+vrmW05LHzOKGBEBlshFr35M1RMZHK 39YgMv8WAHdRvTJSGmfjaQipUf6EThxf6U8lcbM2MprvCLVe2+zsG086sktInls3J0Ax dXScLpi4/zwtaCnotu6zng5hnwKQQH+o7LcIYLnE4diuLKSyPodCAs7X+/y8q2i8lUkh KTIt277AP3UgtAIsG+2zHrGWdhJpYsKF+STBN81XfpP8iUJZngAesABhJKmkPnp4ewlN AeC+0xT6XDsH+2rGor1usm/mFoN4AYqYZtcnlNn76byntbl7P6aLQ4+tl9E5bixlh1jm bekA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=79/BDVQB6iIHA8qtbmo8Z058Jh2Dn0Ccb3iPyejC9bY=; b=pU4NwpMDbPKGe77UmzdxjB8fRhahIqcF8hHRl0emmbUMoOYYCY0v3wNgkxgmF2vt5k pSUbJFGu3+d/oO3sktHQakDKp5Luwp6KczGmSOAiqlZzdFFklLH64f3Qlvt8Vmxd+Pfn m3695oAHyGp/+qfuvSHGedYjBhzIfzVbYqBlYLUuGVsV5ZbLnuig6YrqW3TSE6MSaHHt aKL5TLejEOxWzTQkHwyCzTP+We2k306ELs9uY2uDEce0uvymqx/xUfLsPilyWS7GJkw9 R/1FBU3MJNkEEuRq016vH0JSUYjtXTScKbF5lIH0VL0+BzwLXwLlifGA6arEBiPEcaB7 7S1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tEWbgDWR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v12si798619qto.199.2021.07.28.17.55.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Jul 2021 17:55:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tEWbgDWR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m8uKc-0008RS-LV for patch@linaro.org; Wed, 28 Jul 2021 20:55:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36876) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m8uCW-00049X-7U for qemu-devel@nongnu.org; Wed, 28 Jul 2021 20:47:04 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:41585) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m8uCU-0002TH-Aa for qemu-devel@nongnu.org; Wed, 28 Jul 2021 20:47:03 -0400 Received: by mail-pl1-x635.google.com with SMTP id z3so3537043plg.8 for ; Wed, 28 Jul 2021 17:47:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=79/BDVQB6iIHA8qtbmo8Z058Jh2Dn0Ccb3iPyejC9bY=; b=tEWbgDWR8eofMFVmZhKK3SuV9PmAn+At4HUIlJK5fP3xg4nQfkPr4riek11e1Hjao5 s45wbaPpnUjcXmspC3fqOr6tZ5GWUFo0wqIGjH7vCUwgqL1QXCfo+Rhed51Nk2cZmUmn 0w+gEgq3+Dssn2lDedmB6anQ4JZBoSvryn4wL432NOOfAOFVG40RuKjwJeULji3SYFhF 0HRvYQJOT/Mss0Puscyk61SHxtz9lCzwMMIPaZVUtajVajCxop+G+BRqfFSkVyBrlj2W ufBBhXok/frSEpTzgJMjGoSx4dUebhka/Ey30tzgTtiTk/XPhIugaGiAeedcCYFagAqx 36Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=79/BDVQB6iIHA8qtbmo8Z058Jh2Dn0Ccb3iPyejC9bY=; b=gHsvGmrVRjLoC7kYUz4+rjhKTPdxGhr9KW1PiAoClPYwWHlwmq9IcBcvY70B6tAUvn tGGIjj85t27AxGcv9uvtPs/+kRIQ9kUREhTv0BqwEQJjDARwNR9sfa9f2vzFSORn3hAT 8vBkfFvD0npVa7tGr7PxntFMcTp02fqILmHwrX1A0mB7u/3Yq0V6Q7XvdZpFQXiod/7o 1wJX8B3UJl98aWH1FSuVmE08faJis1f9pHPE1AzAbXal7jsFXrW0CCAy0xX9GZGeCvxR 9Kqihm0n/A2PpE14x1YOanar/MsFcyecRuc2iRPKUj2urXkniVLnzyXKAGcSZ33l10rn 0xlA== X-Gm-Message-State: AOAM5336ooZbvgFUw/zdiM8a7gNPDJGgUqUb2vgUUL/WTpXS6CntCIZP PuW0AtBHmvk/kxDGwCMijIrYGSiHkkswEw== X-Received: by 2002:a17:902:a9c7:b029:12b:349:b318 with SMTP id b7-20020a170902a9c7b029012b0349b318mr2132641plr.13.1627519620840; Wed, 28 Jul 2021 17:47:00 -0700 (PDT) Received: from cloudburst.home (2603-800c-3202-ffa7-dcaa-9e71-a2b2-2604.res6.spectrum.com. [2603:800c:3202:ffa7:dcaa:9e71:a2b2:2604]) by smtp.gmail.com with ESMTPSA id t205sm1305005pfc.32.2021.07.28.17.46.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 17:47:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.2 09/43] target/riscv: Implement do_unaligned_access for user-only Date: Wed, 28 Jul 2021 14:46:13 -1000 Message-Id: <20210729004647.282017-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210729004647.282017-1-richard.henderson@linaro.org> References: <20210729004647.282017-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: qemu-riscv@nongnu.org Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 7 +++++++ target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 8 +++++++- 3 files changed, 15 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Alistair Francis diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 74a9628dc9..0428140d86 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -92,6 +92,13 @@ void cpu_loop(CPURISCVState *env) sigcode = TARGET_SEGV_MAPERR; sigaddr = env->badaddr; break; + case RISCV_EXCP_INST_ADDR_MIS: + case RISCV_EXCP_LOAD_ADDR_MIS: + case RISCV_EXCP_STORE_AMO_ADDR_MIS: + signum = TARGET_SIGBUS; + sigcode = TARGET_BUS_ADRALN; + sigaddr = env->badaddr; + break; case RISCV_EXCP_SEMIHOST: env->gpr[xA0] = do_common_semihosting(cs); env->pc += 4; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 991a6bb760..591d17e62d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -644,11 +644,11 @@ static const struct TCGCPUOps riscv_tcg_ops = { .synchronize_from_tb = riscv_cpu_synchronize_from_tb, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .tlb_fill = riscv_cpu_tlb_fill, + .do_unaligned_access = riscv_cpu_do_unaligned_access, #ifndef CONFIG_USER_ONLY .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, - .do_unaligned_access = riscv_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 968cb8046f..a440b2834f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -727,6 +727,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); } +#endif /* !CONFIG_USER_ONLY */ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, @@ -734,6 +735,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; + switch (access_type) { case MMU_INST_FETCH: cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; @@ -748,11 +750,15 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, g_assert_not_reached(); } env->badaddr = addr; + +#ifdef CONFIG_USER_ONLY + cpu_loop_exit_restore(cs, retaddr); +#else env->two_stage_lookup = riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); riscv_raise_exception(env, cs->exception_index, retaddr); +#endif } -#endif /* !CONFIG_USER_ONLY */ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx,