| Message ID | 20210709042608.883256-7-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/riscv: Use tcg_constant_* | expand |
On Fri, Jul 9, 2021 at 2:39 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > Narrow the scope of t0 in trans_jalr. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_rvi.c.inc | 25 ++++++++++--------------- > 1 file changed, 10 insertions(+), 15 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc > index 6e736c9d0d..a603925637 100644 > --- a/target/riscv/insn_trans/trans_rvi.c.inc > +++ b/target/riscv/insn_trans/trans_rvi.c.inc > @@ -54,24 +54,25 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a) > > static bool trans_jalr(DisasContext *ctx, arg_jalr *a) > { > - /* no chaining with JALR */ > TCGLabel *misaligned = NULL; > - TCGv t0 = tcg_temp_new(); > > - > - gen_get_gpr(cpu_pc, a->rs1); > - tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm); > + tcg_gen_addi_tl(cpu_pc, gpr_src(ctx, a->rs1), a->imm); > tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); > > if (!has_ext(ctx, RVC)) { > + TCGv t0 = tcg_temp_new(); > + > misaligned = gen_new_label(); > tcg_gen_andi_tl(t0, cpu_pc, 0x2); > tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned); > + tcg_temp_free(t0); > } > > if (a->rd != 0) { > tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn); > } > + > + /* No chaining with JALR. */ > lookup_and_goto_ptr(ctx); > > if (misaligned) { > @@ -80,21 +81,18 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) > } > ctx->base.is_jmp = DISAS_NORETURN; > > - tcg_temp_free(t0); > return true; > } > > static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) > { > TCGLabel *l = gen_new_label(); > - TCGv source1, source2; > - source1 = tcg_temp_new(); > - source2 = tcg_temp_new(); > - gen_get_gpr(source1, a->rs1); > - gen_get_gpr(source2, a->rs2); > + TCGv src1 = gpr_src(ctx, a->rs1); > + TCGv src2 = gpr_src(ctx, a->rs2); > > - tcg_gen_brcond_tl(cond, source1, source2, l); > + tcg_gen_brcond_tl(cond, src1, src2, l); > gen_goto_tb(ctx, 1, ctx->pc_succ_insn); > + > gen_set_label(l); /* branch taken */ > > if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) { > @@ -105,9 +103,6 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) > } > ctx->base.is_jmp = DISAS_NORETURN; > > - tcg_temp_free(source1); > - tcg_temp_free(source2); > - > return true; > } > > -- > 2.25.1 > >
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 6e736c9d0d..a603925637 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -54,24 +54,25 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a) static bool trans_jalr(DisasContext *ctx, arg_jalr *a) { - /* no chaining with JALR */ TCGLabel *misaligned = NULL; - TCGv t0 = tcg_temp_new(); - - gen_get_gpr(cpu_pc, a->rs1); - tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm); + tcg_gen_addi_tl(cpu_pc, gpr_src(ctx, a->rs1), a->imm); tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); if (!has_ext(ctx, RVC)) { + TCGv t0 = tcg_temp_new(); + misaligned = gen_new_label(); tcg_gen_andi_tl(t0, cpu_pc, 0x2); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned); + tcg_temp_free(t0); } if (a->rd != 0) { tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn); } + + /* No chaining with JALR. */ lookup_and_goto_ptr(ctx); if (misaligned) { @@ -80,21 +81,18 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) } ctx->base.is_jmp = DISAS_NORETURN; - tcg_temp_free(t0); return true; } static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) { TCGLabel *l = gen_new_label(); - TCGv source1, source2; - source1 = tcg_temp_new(); - source2 = tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + TCGv src1 = gpr_src(ctx, a->rs1); + TCGv src2 = gpr_src(ctx, a->rs2); - tcg_gen_brcond_tl(cond, source1, source2, l); + tcg_gen_brcond_tl(cond, src1, src2, l); gen_goto_tb(ctx, 1, ctx->pc_succ_insn); + gen_set_label(l); /* branch taken */ if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) { @@ -105,9 +103,6 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) } ctx->base.is_jmp = DISAS_NORETURN; - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; }
Narrow the scope of t0 in trans_jalr. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/insn_trans/trans_rvi.c.inc | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) -- 2.25.1