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[209.51.188.17]) by mx.google.com with ESMTPS id t11si2532784qkg.335.2021.07.08.14.39.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Jul 2021 14:39:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tyIOlqKF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1bjn-0008Qf-Eh for patch@linaro.org; Thu, 08 Jul 2021 17:39:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54400) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1bib-0008PZ-C5 for qemu-devel@nongnu.org; Thu, 08 Jul 2021 17:38:01 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:45627) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m1biY-0008LW-Tq for qemu-devel@nongnu.org; Thu, 08 Jul 2021 17:38:01 -0400 Received: by mail-pf1-x434.google.com with SMTP id q10so6753456pfj.12 for ; Thu, 08 Jul 2021 14:37:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Kl6JnE7xohFEPb4Uv6igXK9acm2oRLRWePiQGSpIWy4=; b=tyIOlqKFHNiQ3qDfZ+BfKFbFyuhmaA2T+sVffHQvfZoEv7iVXeFKd5uYuzXQnB8v6L rD7rD65ESGk0zRdZonAApD00cqPVKYeVjRYBHauqfNyi0ogrpOjgN+D6xnK9L39JlWG8 8hjoapyrEEOJzRhhpXIrOfpx4N3NaGm+c6+HYFu6j3ckUgesXpLlntW/08GSsyeFBxWw gRzcmX3HQ6BLkHRFIU8mC/rqugA/NTz5cREsLm3Vn6dN7WpJ3p8CXB+wuCkEyGEgADs7 UBdat+nVT1ovbKKhBS1RdtdqFdLR8yxGPV0ATAdl4+gBF6diTaxhLh0y/HdtdqjLsqPx nQwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kl6JnE7xohFEPb4Uv6igXK9acm2oRLRWePiQGSpIWy4=; b=cUpE7PNXIyOd7u5X/jIP0I+XqIPE9CVHJTuePOWSWHY+HeGPHa9BC1ttgLGVW2IHIS BmRcZamqTmjMbX9BbzKKZgV+UGVgALird6FqnCCaE5jgHekARdS9/7+St1X3vw8ejnyT emlis860pqoXOkd0/K57Ph7meJWsQrxFKuX09QKA4gS6vcBdygLNMUE5yQEy3jxUwJlS sJfjG+UDOx0bFcXArUrhGS7Me3BffInnbP6WIH95k3KJAnPPBkErg0xBAZulQrKcphLq FI12kHeWwH+hj6h+jgG6lcMxhm2ug7DP4+89OrLHitEFHywJH4ytK9/gcPf4rvHEULXv lNJA== X-Gm-Message-State: AOAM530GZ+VdRx2K0GT4D52AIXB3XvpmSawMo6GF3ywWQC8GOjtwBabq 3fbBuuiGDvidkeandZoOM8WdYFxn1HmD4g== X-Received: by 2002:aa7:8158:0:b029:301:8d0b:3d09 with SMTP id d24-20020aa781580000b02903018d0b3d09mr32995086pfn.48.1625780277694; Thu, 08 Jul 2021 14:37:57 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id g27sm4322800pgl.19.2021.07.08.14.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 14:37:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/4] target/openrisc: Cache constant 0 in DisasContext Date: Thu, 8 Jul 2021 14:37:53 -0700 Message-Id: <20210708213754.830485-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210708213754.830485-1-richard.henderson@linaro.org> References: <20210708213754.830485-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We are virtually certain to have fetched constant 0 once, at the beginning of the TB, so we might as well use it elsewhere. Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stafford Horne diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 96df513fd3..3d86bdffaa 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -53,6 +53,8 @@ typedef struct DisasContext { /* The temporary corresponding to register 0 for this compilation. */ TCGv R0; + /* The constant zero. */ + TCGv zero; } DisasContext; static inline bool is_user(DisasContext *dc) @@ -537,10 +539,8 @@ static bool trans_l_extbz(DisasContext *dc, arg_da *a) static bool trans_l_cmov(DisasContext *dc, arg_dab *a) { - TCGv zero = tcg_constant_tl(0); - check_r0_write(dc, a->d); - tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, zero, + tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, dc->zero, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } @@ -631,9 +631,8 @@ static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond) target_ulong tmp_pc = dc->base.pc_next + a->n * 4; TCGv t_next = tcg_constant_tl(dc->base.pc_next + 8); TCGv t_true = tcg_constant_tl(tmp_pc); - TCGv t_zero = tcg_constant_tl(0); - tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, t_zero, t_true, t_next); + tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, dc->zero, t_true, t_next); dc->delayed_branch = 2; } @@ -1595,8 +1594,9 @@ static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs) /* Allow the TCG optimizer to see that R0 == 0, when it's true, which is the common case. */ + dc->zero = tcg_constant_tl(0); if (dc->tb_flags & TB_FLAGS_R0_0) { - dc->R0 = tcg_constant_tl(0); + dc->R0 = dc->zero; } else { dc->R0 = cpu_regs[0]; }