@@ -344,3 +344,62 @@ which will output an execution trace following this structure::
0, 0xd32, 0xf9893014, "adds r0, #0x14"
0, 0xd34, 0xf9c8f000, "bl #0x10c8"
0, 0x10c8, 0xfff96c43, "ldr r3, [r0, #0x44]", load, 0x200000e4, RAM
+
+- contrib/plugins/cache
+
+Cache modelling plugin that measures the performance of a given cache
+configuration when a given working set is run::
+
+ qemu-x86_64 -plugin ./contrib/plugins/libcache.so \
+ -d plugin -D cache.log ./tests/tcg/x86_64-linux-user/float_convs
+
+will report the following::
+
+ Data accesses: 996479, Misses: 507
+ Miss rate: 0.050879%
+
+ Instruction accesses: 2641737, Misses: 18617
+ Miss rate: 0.704726%
+
+ address, data misses, instruction
+ 0x424f1e (_int_malloc), 109, movq %rax, 8(%rcx)
+ 0x41f395 (_IO_default_xsputn), 49, movb %dl, (%rdi, %rax)
+ 0x42584d (ptmalloc_init.part.0), 33, movaps %xmm0, (%rax)
+ 0x454d48 (__tunables_init), 20, cmpb $0, (%r8)
+ ...
+
+ address, fetch misses, instruction
+ 0x4160a0 (__vfprintf_internal), 744, movl $1, %ebx
+ 0x41f0a0 (_IO_setb), 744, endbr64
+ 0x415882 (__vfprintf_internal), 744, movq %r12, %rdi
+ 0x4268a0 (__malloc), 696, andq $0xfffffffffffffff0, %rax
+ ...
+
+The plugin has a number of arguments, all of them are optional:
+
+ * arg="limit=N"
+
+ Print top N icache and dcache thrashing instructions along with their
+ address, number of misses, and its disassembly. (default: 32)
+
+ * arg="icachesize=N"
+ * arg="iblksize=B"
+ * arg="iassoc=A"
+
+ Instruction cache configuration arguments. They specify the cache size, block
+ size, and associativity of the instruction cache, respectively.
+ (default: N = 16384, B = 64, A = 8)
+
+ * arg="dcachesize=N"
+ * arg="dblksize=B"
+ * arg="dassoc=A"
+
+ Data cache configuration arguments. They specify the cache size, block size,
+ and associativity of the data cache, respectively.
+ (default: N = 16384, B = 64, A = 8)
+
+ * arg="evict=POLICY"
+
+ Sets the eviction policy to POLICY. Available policies are: :code:`lru`,
+ :code:`fifo`, and :code:`rand`. The plugin will use the specified policy for
+ both instruction and data caches. (default: POLICY = :code:`lru`)