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[PULL,14/33] tcg/tci: Remove tci_write_reg

Message ID 20210619181452.877683-15-richard.henderson@linaro.org
State Accepted
Commit 7e00a0800051655e6fdd85ad5dd6fcadafc2dc47
Headers show
Series tcg patch queue | expand

Commit Message

Richard Henderson June 19, 2021, 6:14 p.m. UTC 
Inline it into its one caller, tci_write_reg64.
Drop the asserts that are redundant with tcg_read_r.

Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 tcg/tci.c | 13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

-- 
2.25.1
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Patch

diff --git a/tcg/tci.c b/tcg/tci.c
index dfaa9c0fa0..613b94997c 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -38,20 +38,11 @@ 
 
 __thread uintptr_t tci_tb_ptr;
 
-static void
-tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
-{
-    tci_assert(index < TCG_TARGET_NB_REGS);
-    tci_assert(index != TCG_AREG0);
-    tci_assert(index != TCG_REG_CALL_STACK);
-    regs[index] = value;
-}
-
 static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
                             uint32_t low_index, uint64_t value)
 {
-    tci_write_reg(regs, low_index, value);
-    tci_write_reg(regs, high_index, value >> 32);
+    regs[low_index] = value;
+    regs[high_index] = value >> 32;
 }
 
 /* Create a 64 bit value from two 32 bit values. */