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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id a129sm2422599pfa.118.2021.06.04.13.12.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 13:12:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec Date: Fri, 4 Jun 2021 13:12:04 -0700 Message-Id: <20210604201210.920136-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604201210.920136-1-richard.henderson@linaro.org> References: <20210604201210.920136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index cfbadad72c..94d768f249 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -166,7 +166,7 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 -#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_bitsel_vec 0 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index d21aaab6f7..b94e6ed0f3 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -183,6 +183,7 @@ typedef enum { INSN_VORN = 0xf2300110, INSN_VORR = 0xf2200110, INSN_VSUB = 0xf3000800, + INSN_VMUL = 0xf2000910, INSN_VABS = 0xf3b10300, INSN_VMVN = 0xf3b00580, @@ -2394,6 +2395,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) return C_O1_I1(w, w); case INDEX_op_dup2_vec: case INDEX_op_add_vec: + case INDEX_op_mul_vec: case INDEX_op_sub_vec: case INDEX_op_xor_vec: return C_O1_I2(w, w, w); @@ -2755,6 +2757,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_add_vec: tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2); return; + case INDEX_op_mul_vec: + tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2); + return; case INDEX_op_sub_vec: tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); return; @@ -2871,6 +2876,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) return 1; case INDEX_op_abs_vec: case INDEX_op_cmp_vec: + case INDEX_op_mul_vec: case INDEX_op_neg_vec: return vece < MO_64; default: