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[209.51.188.17]) by mx.google.com with ESMTPS id m13si2736289vsk.332.2021.06.04.09.27.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 04 Jun 2021 09:27:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zqBSpXrV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCf9-00038K-FB for patch@linaro.org; Fri, 04 Jun 2021 12:27:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48540) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCHy-0008Ec-B9 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:17 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:45608) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHZ-0005nE-DO for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:10 -0400 Received: by mail-wm1-x335.google.com with SMTP id v206-20020a1cded70000b02901a586d3fa23so1629616wmg.4 for ; Fri, 04 Jun 2021 09:02:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1M9DSMG90oxpkIftDhmS6X3YTXP3prGe70gnCR2W/W0=; b=zqBSpXrVgFZHYH3MLkjTX40nmjnrTG1dVG15IOZoP5dtK/dTwoU1jDxFRaYDKemzjC MDqy4P4LuUHz2d5UIuYPPW32W/5YTO1VP426Uh3Fi/MF6mqHWvHloBrAktplt+UJcyTa LJLwC820GlaD1qcJsIwWs2wz9xZdgA2d1JDUAzn4J2pDppTmSWWqWE5n09urgB1qjOTF j62jYZqYHOVjaSGVZyEs/BiG0zUyg66K3o8IlXeWfrtmQM8QvdanolHWNYiS2EE/RK0i cWBwB4HUPVu/ig3J8CPLA/aqoc6BnjR3DoTtP7hlmWNwOmCHyCg/lDO8sMMKGPdKSaYr TvbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1M9DSMG90oxpkIftDhmS6X3YTXP3prGe70gnCR2W/W0=; b=GsDEQTcRCNCz7zFUMhbHXxRqGoMtw/w3HbO1TGvQEGrHcQg2XwyqC4d6RinViB1Wyz +8LwVhvy9RSPR8/qFJ2JPeeRC5stZG7jtJKy3cK4p4a8H2g9XR03gJxgXulh0pd82i5V W0jqEmAuXvtvCeLwx8QXtGibIwpxf7vFUjHSz0ShLRW6VuKZFKWM3W1FONAdC2cryv/K SVRHd6bJqIfhc2OizxQrHqZ894Pdj/2zrHUk6+8ua8hBwbDrtz3pPjmhKyK3jZMoqhYR MfumONqaCOe3mKgtLeI7bRiSt9gB4CDdxsd0rmfwDLgg0rfLno4D14eg1KEpd7BVhl4s TTFw== X-Gm-Message-State: AOAM531VYAU0NJxJmC4riQ0nRSr/E2vOfyRMu9EZ22dLHRTo9rjF4M3y LW0MQZcyYrfdKqNRk6Urk3iXYg== X-Received: by 2002:a7b:c041:: with SMTP id u1mr4237576wmc.95.1622822567983; Fri, 04 Jun 2021 09:02:47 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id s62sm9232329wms.13.2021.06.04.09.02.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 502211FFD2; Fri, 4 Jun 2021 16:53:20 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 61/99] target/arm: remove broad "else" statements when checking accels Date: Fri, 4 Jun 2021 16:52:34 +0100 Message-Id: <20210604155312.15902-62-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Stefano Stabellini , Julien Grall , Olaf Hering , qemu-arm@nongnu.org, Claudio Fontana , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Claudio Fontana There might be more than just KVM and TCG in the future, so where appropriate, replace broad "else" statements with the appropriate if (accel_enabled()) check. Also invert some checks for !kvm_enabled() or !tcg_enabled() where it seems appropriate to do so. Note that to make qtest happy we need to perform gpio initialization in the qtest_enabled() case as well. Hopefully we do not break any Xen stuff. Signed-off-by: Claudio Fontana Cc: Julien Grall Cc: Stefano Stabellini Cc: Olaf Hering Cc: Alex Bennée Signed-off-by: Alex Bennée --- target/arm/cpu.c | 9 +++++---- target/arm/cpu64.c | 9 +++++---- target/arm/machine.c | 18 ++++++------------ 3 files changed, 16 insertions(+), 20 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7e3726ff00..57f975f5dc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -37,6 +37,7 @@ #endif #include "sysemu/tcg.h" +#include "sysemu/qtest.h" #include "kvm/kvm_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" @@ -564,7 +565,7 @@ static void arm_cpu_initfn(Object *obj) * the same interface as non-KVM CPUs. */ qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); - } else { + } else if (tcg_enabled() || qtest_enabled()) { qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); } @@ -741,14 +742,14 @@ void arm_cpu_post_init(Object *obj) ? cpu_isar_feature(aa64_fp_simd, cpu) : cpu_isar_feature(aa32_vfp, cpu)) { cpu->has_vfp = true; - if (!kvm_enabled()) { + if (tcg_enabled()) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); } } if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { cpu->has_neon = true; - if (!kvm_enabled()) { + if (tcg_enabled()) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); } } @@ -849,7 +850,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) * We have not registered the cpu properties when KVM * is in use, so the user will not be able to set them. */ - if (!kvm_enabled()) { + if (tcg_enabled()) { arm_cpu_pauth_finalize(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a8ff1994ca..e3d818275c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "cpu32.h" #include "qemu/module.h" +#include "sysemu/tcg.h" #include "sysemu/kvm.h" #include "kvm/kvm_arm.h" #include "qapi/visitor.h" @@ -297,7 +298,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) */ bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq); bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); - } else { + } else if (tcg_enabled()) { /* Propagate enabled bits down through required powers-of-two. */ for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { if (!test_bit(vq - 1, cpu->sve_vq_init)) { @@ -334,7 +335,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) "vector length must be enabled.\n"); return; } - } else { + } else if (tcg_enabled()) { /* Disabling a power-of-two disables all larger lengths. */ if (test_bit(0, cpu->sve_vq_init)) { error_setg(errp, "cannot disable sve128"); @@ -416,7 +417,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) } return; } - } else { + } else if (tcg_enabled()) { /* Ensure all required powers-of-two are enabled. */ for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { if (!test_bit(vq - 1, cpu->sve_vq_map)) { @@ -610,7 +611,7 @@ static void aarch64_max_initfn(Object *obj) if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); - } else { + } else if (tcg_enabled()) { uint64_t t; uint32_t u; aarch64_a57_initfn(obj); diff --git a/target/arm/machine.c b/target/arm/machine.c index 595ab94237..4acdccc22d 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -638,9 +638,11 @@ static int cpu_pre_save(void *opaque) if (tcg_enabled()) { pmu_op_start(&cpu->env); - } - - if (kvm_enabled()) { + if (!write_cpustate_to_list(cpu, false)) { + /* This should never fail. */ + abort(); + } + } else if (kvm_enabled()) { if (!write_kvmstate_to_list(cpu)) { /* This should never fail */ abort(); @@ -651,11 +653,6 @@ static int cpu_pre_save(void *opaque) * write_kvmstate_to_list() */ kvm_arm_cpu_pre_save(cpu); - } else { - if (!write_cpustate_to_list(cpu, false)) { - /* This should never fail. */ - abort(); - } } cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; @@ -754,13 +751,10 @@ static int cpu_post_load(void *opaque, int version_id) */ write_list_to_cpustate(cpu); kvm_arm_cpu_post_load(cpu); - } else { + } else if (tcg_enabled()) { if (!write_list_to_cpustate(cpu)) { return -1; } - } - - if (tcg_enabled()) { hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu);