From patchwork Fri Jun 4 15:52:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 454141 Delivered-To: patch@linaro.org Received: by 2002:a02:735a:0:0:0:0:0 with SMTP id a26csp621871jae; Fri, 4 Jun 2021 10:40:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwAJKrxVVViZDhttRhmAWXvIX6+H0a0IQPOV8Jg593YXd53IHVqLYoOl1D78I8O8L2s7R5Y X-Received: by 2002:a05:6e02:de9:: with SMTP id m9mr5041464ilj.89.1622828459407; Fri, 04 Jun 2021 10:40:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622828459; cv=none; d=google.com; s=arc-20160816; b=wmfsy7YH3BfRJhAEh2o/K5Na/vkTOviO67Bz9FQac75ygxET942Ij3P9kigJldn3Hm SsbG8tl6iALJRndKnWjgXW/XSlEZmac87lW57ZXw0XOc80pLabf9dcvKXOiKM7qedaLa /i9451EgZzYtCDV6bj5SEZF0U2e4kX6cUK3FfFbggYvKMdfdnU8hbdGuH8v/n6JJiA7Q gAEN7Q5FtcF1vymCLwFizceXMXXm6wKNpJW3h+ozMJL6pTcek/0ZTr1VMeJaWLAiE+9K LtqDpynm/PeZ5jvUktak79daVq9OrOv4EsKWPuN9BGG62UHasxl+BX5MC87udAb0mpXT GoTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=05nkHLjcRHyfDukFJajvGPGtE1+ijrzLS+mVjmVHqf8=; b=ovyz9Xs9ZmGkwCRA8VTOjWPbKpApL8J4XQ2wP53kesPbuaARZPzStbW3OtjMPgx14+ qq5lrhJrei0OXZihbUZ2sI9cj5VrugDLk/qNbz7TADaclPc+9C2m0+SKNJS/AgLA9d8L jglmJqjSre2B3NCzJGja8j0fPo7F15TiguzLFnOFfJ2zD8f2mfcZHODfbl+m89VXAC5i 2q4Cf+2d7rHS3mvrcS3oSyUllQi1GD8gKWASjtGMEm2VnHrepqe3XkvUl0PhGykKp6f+ Yn+SwPoyoyQxceqTU4IwXA7WerK6HfkWaZylp2wntLuGLltpf3OYw2CElQfar3d65YZ9 JO0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DodAKl7e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h10si8028750ili.90.2021.06.04.10.40.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 04 Jun 2021 10:40:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DodAKl7e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58050 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDoY-0002w3-SH for patch@linaro.org; Fri, 04 Jun 2021 13:40:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpDNY-0000TB-0L for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:13:04 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:40637) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpDNR-00028f-QQ for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:13:03 -0400 Received: by mail-wr1-x42d.google.com with SMTP id y7so5387707wrh.7 for ; Fri, 04 Jun 2021 10:12:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=05nkHLjcRHyfDukFJajvGPGtE1+ijrzLS+mVjmVHqf8=; b=DodAKl7esocnjjL/SdHyoskpdivSLAuDP3NAJ35wJcmxAE4rrmKaa80TM3hjYhxRHN QFmSCWX/2cRPrLgWyhCMUdfn4CB4Z1omc9RE4J7Ajdmvx7r42a4x+ZpVzxP1lggrmOjV m2alL0J3LugU5AD0DUBWpMCt1J5iQ7nXFe/yqmelp7axmiiGCQm5kWGoKgrm2fbwxLn0 3RX7LhRBGrH+6BOZde8sKNjrtj1r3mFcZ/YufbJUt5BMz7u861Bhlo2+19KPZxYHc6xa fJuUSElnLblI87nvh+vacSW5fBsdHUnzIu78FA3MW0/Sk+RH4qp2ZQBkoe05NITs1B5R GtIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=05nkHLjcRHyfDukFJajvGPGtE1+ijrzLS+mVjmVHqf8=; b=Bc33fV12hdXf1bNSuTwWDBD4VB9q6A9JVrxTnOaAdzHR3KWdCnUUkQKfsew7l++tad Bw/u82sZM/+Qa799MyT+UgeQv9uDRxcZsYodFNcpcLd5wwaSmWXnVmFuuD4Yev+FqFoe 9CCatuQx0wy4jM8KQdYAXS3mfgKPMJ9IJYy/1PuAnwlztoqoAx6txLciwjAVTAxudHEL KzM1uCch0PCryZ+iP2+qU/yzSph/KYxaAHAKz8/vV9V+XyN8IX3oJ517KmMZVHiPa5pP Babkc59f04m4Qfws7qajcU3MpUzYMwZGs7fpyvVAOizUvO1S4D91vfU8Zjr/2beTwuru 76Lw== X-Gm-Message-State: AOAM531tMs0s1x123I/jcyGFWHc7SuNElJTbthoOP4JSRbIRbbfGIELp tEGkIYOrxnSeO7BoNu0IVcW9aQ== X-Received: by 2002:adf:f382:: with SMTP id m2mr4983685wro.394.1622826776475; Fri, 04 Jun 2021 10:12:56 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id q20sm9145301wrf.45.2021.06.04.10.12.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 10:12:46 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 73FBC1FFC4; Fri, 4 Jun 2021 16:53:18 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 45/99] target/arm: move sve_exception_el out of TCG helpers Date: Fri, 4 Jun 2021 16:52:18 +0100 Message-Id: <20210604155312.15902-46-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Claudio Fontana we need this for KVM too. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée --- target/arm/cpu-sysemu.c | 62 +++++++++++++++++++++++++++++++++++++++ target/arm/cpu-user.c | 5 ++++ target/arm/tcg/helper.c | 64 ----------------------------------------- 3 files changed, 67 insertions(+), 64 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index 7a314bf805..7cc721fe68 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -348,3 +348,65 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[15] = env->pc; } + +/* + * Return the exception level to which exceptions should be taken + * via SVEAccessTrap. If an exception should be routed through + * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should + * take care of raising that exception. + * C.f. the ARM pseudocode function CheckSVEEnabled. + */ +int sve_exception_el(CPUARMState *env, int el) +{ + uint64_t hcr_el2 = arm_hcr_el2_eff(env); + + if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { + bool disabled = false; + + /* + * The CPACR.ZEN controls traps to EL1: + * 0, 2 : trap EL0 and EL1 accesses + * 1 : trap only EL0 accesses + * 3 : trap no accesses + */ + if (!extract32(env->cp15.cpacr_el1, 16, 1)) { + disabled = true; + } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) { + disabled = el == 0; + } + if (disabled) { + /* route_to_el2 */ + return hcr_el2 & HCR_TGE ? 2 : 1; + } + + /* Check CPACR.FPEN. */ + if (!extract32(env->cp15.cpacr_el1, 20, 1)) { + disabled = true; + } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) { + disabled = el == 0; + } + if (disabled) { + return 0; + } + } + + /* + * CPTR_EL2. Since TZ and TFP are positive, + * they will be zero when EL2 is not present. + */ + if (el <= 2 && arm_is_el2_enabled(env)) { + if (env->cp15.cptr_el[2] & CPTR_TZ) { + return 2; + } + if (env->cp15.cptr_el[2] & CPTR_TFP) { + return 0; + } + } + + /* CPTR_EL3. Since EZ is negative we must check for EL3. */ + if (arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.cptr_el[3] & CPTR_EZ)) { + return 3; + } + return 0; +} diff --git a/target/arm/cpu-user.c b/target/arm/cpu-user.c index 0225089e46..39093ade76 100644 --- a/target/arm/cpu-user.c +++ b/target/arm/cpu-user.c @@ -33,3 +33,8 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, { return 1; } + +int sve_exception_el(CPUARMState *env, int el) +{ + return 0; +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 1c69a69d5a..8372089260 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -261,70 +261,6 @@ static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) } #endif /* TARGET_AARCH64 */ -/* - * Return the exception level to which exceptions should be taken - * via SVEAccessTrap. If an exception should be routed through - * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should - * take care of raising that exception. - * C.f. the ARM pseudocode function CheckSVEEnabled. - */ -int sve_exception_el(CPUARMState *env, int el) -{ -#ifndef CONFIG_USER_ONLY - uint64_t hcr_el2 = arm_hcr_el2_eff(env); - - if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { - bool disabled = false; - - /* - * The CPACR.ZEN controls traps to EL1: - * 0, 2 : trap EL0 and EL1 accesses - * 1 : trap only EL0 accesses - * 3 : trap no accesses - */ - if (!extract32(env->cp15.cpacr_el1, 16, 1)) { - disabled = true; - } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) { - disabled = el == 0; - } - if (disabled) { - /* route_to_el2 */ - return hcr_el2 & HCR_TGE ? 2 : 1; - } - - /* Check CPACR.FPEN. */ - if (!extract32(env->cp15.cpacr_el1, 20, 1)) { - disabled = true; - } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) { - disabled = el == 0; - } - if (disabled) { - return 0; - } - } - - /* - * CPTR_EL2. Since TZ and TFP are positive, - * they will be zero when EL2 is not present. - */ - if (el <= 2 && arm_is_el2_enabled(env)) { - if (env->cp15.cptr_el[2] & CPTR_TZ) { - return 2; - } - if (env->cp15.cptr_el[2] & CPTR_TFP) { - return 0; - } - } - - /* CPTR_EL3. Since EZ is negative we must check for EL3. */ - if (arm_feature(env, ARM_FEATURE_EL3) - && !(env->cp15.cptr_el[3] & CPTR_EZ)) { - return 3; - } -#endif - return 0; -} - void hw_watchpoint_update(ARMCPU *cpu, int n) { CPUARMState *env = &cpu->env;