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[209.51.188.17]) by mx.google.com with ESMTPS id k20si5063293ejd.293.2021.06.04.09.03.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 04 Jun 2021 09:03:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WXrKnXgh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46836 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCI4-0007C9-AG for patch@linaro.org; Fri, 04 Jun 2021 12:03:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44610) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8d-000331-9c for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:35 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:36842) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8Z-00006V-LB for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:34 -0400 Received: by mail-wr1-x434.google.com with SMTP id n4so9814581wrw.3 for ; Fri, 04 Jun 2021 08:53:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bGZvEWP0B7XQQEsHoRPrpycuhOjRaiqhP5MCalZexp8=; b=WXrKnXghbHEvw8Vgiq01+e7x8S36P2nbON4QAdKLwgJKvKlXFLZL2t966Npejniae1 kmgtm8uPNGRTwLthfl+0SYlhYwqJ+PI8bI2QsGTUQodygLZHtFTJwsm5wMAXUEx4zKQV k39dJMQ7hLKZ+DAbpot18+mGaLE2QViRkqFgWIUXDqFNMw7861ZL4OtZNqGR6khhc0EA iR5wqCSgX/Hcefcczp7oVSQBjHODyHzSf/Cnfz+oIODZB9yB0GbGKd+H+A5Us597HxLm nlBc6yAyrRjGezhaxh6rRXmL/aCBRz1Slqtq35LlPbThTgqAv/oyZkM080QC9TnX7lnW 3/Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bGZvEWP0B7XQQEsHoRPrpycuhOjRaiqhP5MCalZexp8=; b=QGbQPD698dcUNSlcXEGoPoyEeKrWIy13ZxJQlui0K67WFIG0tLIr0rJqYvxaWLw7e2 St8WZuvUhhWKwBWEAhVYTp28AV5tkehMniCC30zQ7F6D/wMxgH9SnVxxhEvhXCvhqy7y 5ub7rJToAwagCFtP8Jpe2BLUxEZ4xKm897we2DlSfziK9G0PVMOg92lMyyfJYcCaKdqr CJIOonva2zzleXGy7Z1rlPbSifni17s6WHEnZ0dhKHBEehUtteWashhhnNwTM7erK0Ra FCoU1Diu9YOilf3ko5s/qyOJmCkIuumVPuCuiWDzumpqATHSMwju3BjHnn28A4MrRCgg 3Idw== X-Gm-Message-State: AOAM533fTeLY4H+SQkD8lnbaAyNU0mKBSuNEYEgJptJKs7/CQJAZkKB/ XZyXgqccOMKa79iwbwlTruihiw== X-Received: by 2002:a5d:54c8:: with SMTP id x8mr4706349wrv.109.1622822010020; Fri, 04 Jun 2021 08:53:30 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id g11sm6873579wri.59.2021.06.04.08.53.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:24 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A88F91FF9C; Fri, 4 Jun 2021 16:53:13 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 13/99] meson: add target_user_arch Date: Fri, 4 Jun 2021 16:51:46 +0100 Message-Id: <20210604155312.15902-14-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Cornelia Huck , David Hildenbrand , Bin Meng , Mark Cave-Ayland , Max Filippov , Taylor Simpson , Alistair Francis , "Edgar E. Iglesias" , Marek Vasut , Yoshinori Sato , Claudio Fontana , "open list:PowerPC TCG CPUs" , Artyom Tarasenko , Thomas Huth , Richard Henderson , Greg Kurz , "open list:S390 general arch..." , qemu-arm@nongnu.org, Stafford Horne , =?utf-8?q?Alex_Benn=C3=A9e?= , David Gibson , "open list:RISC-V TCG CPUs" , Bastian Koppelmann , Chris Wulff , Laurent Vivier , Palmer Dabbelt Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Claudio Fontana the lack of target_user_arch makes it hard to fully leverage the build system in order to separate user code from sysemu code. Provide it, so that we can avoid the proliferation of #ifdef in target code. Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée [claudio: added changes for new target hexagon] Signed-off-by: Claudio Fontana Signed-off-by: Alex Bennée --- v15 - remove duplicate ss.source_set for mips --- target/alpha/meson.build | 3 +++ target/arm/meson.build | 2 ++ target/cris/meson.build | 3 +++ target/hexagon/meson.build | 3 +++ target/hppa/meson.build | 3 +++ target/m68k/meson.build | 3 +++ target/microblaze/meson.build | 3 +++ target/nios2/meson.build | 3 +++ target/openrisc/meson.build | 3 +++ target/ppc/meson.build | 3 +++ target/riscv/meson.build | 3 +++ target/s390x/meson.build | 3 +++ target/sh4/meson.build | 3 +++ target/sparc/meson.build | 3 +++ target/tricore/meson.build | 3 +++ target/xtensa/meson.build | 3 +++ 16 files changed, 47 insertions(+) -- 2.20.1 diff --git a/target/alpha/meson.build b/target/alpha/meson.build index 1aec55abb4..1b0555d3ee 100644 --- a/target/alpha/meson.build +++ b/target/alpha/meson.build @@ -14,5 +14,8 @@ alpha_ss.add(files( alpha_softmmu_ss = ss.source_set() alpha_softmmu_ss.add(files('machine.c')) +alpha_user_ss = ss.source_set() + target_arch += {'alpha': alpha_ss} target_softmmu_arch += {'alpha': alpha_softmmu_ss} +target_user_arch += {'alpha': alpha_user_ss} diff --git a/target/arm/meson.build b/target/arm/meson.build index 5bfaf43b50..6106d24665 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -56,6 +56,8 @@ arm_softmmu_ss.add(files( 'monitor.c', 'psci.c', )) +arm_user_ss = ss.source_set() target_arch += {'arm': arm_ss} target_softmmu_arch += {'arm': arm_softmmu_ss} +target_user_arch += {'arm': arm_user_ss} diff --git a/target/cris/meson.build b/target/cris/meson.build index 67c3793c85..7fd81e0348 100644 --- a/target/cris/meson.build +++ b/target/cris/meson.build @@ -10,5 +10,8 @@ cris_ss.add(files( cris_softmmu_ss = ss.source_set() cris_softmmu_ss.add(files('mmu.c', 'machine.c')) +cris_user_ss = ss.source_set() + target_arch += {'cris': cris_ss} target_softmmu_arch += {'cris': cris_softmmu_ss} +target_user_arch += {'cris': cris_user_ss} diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index 6fd9360b74..fe232810ab 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -175,4 +175,7 @@ hexagon_ss.add(files( 'fma_emu.c', )) +hexagon_user_ss = ss.source_set() + target_arch += {'hexagon': hexagon_ss} +target_user_arch += {'hexagon': hexagon_user_ss} diff --git a/target/hppa/meson.build b/target/hppa/meson.build index 8a7ff82efc..85ad314671 100644 --- a/target/hppa/meson.build +++ b/target/hppa/meson.build @@ -15,5 +15,8 @@ hppa_ss.add(files( hppa_softmmu_ss = ss.source_set() hppa_softmmu_ss.add(files('machine.c')) +hppa_user_ss = ss.source_set() + target_arch += {'hppa': hppa_ss} target_softmmu_arch += {'hppa': hppa_softmmu_ss} +target_user_arch += {'hppa': hppa_user_ss} diff --git a/target/m68k/meson.build b/target/m68k/meson.build index 05cd9fbd1e..b507682684 100644 --- a/target/m68k/meson.build +++ b/target/m68k/meson.build @@ -13,5 +13,8 @@ m68k_ss.add(files( m68k_softmmu_ss = ss.source_set() m68k_softmmu_ss.add(files('monitor.c')) +m68k_user_ss = ss.source_set() + target_arch += {'m68k': m68k_ss} target_softmmu_arch += {'m68k': m68k_softmmu_ss} +target_user_arch += {'m68k': m68k_user_ss} diff --git a/target/microblaze/meson.build b/target/microblaze/meson.build index 05ee0ec163..52d8fcb0a3 100644 --- a/target/microblaze/meson.build +++ b/target/microblaze/meson.build @@ -16,5 +16,8 @@ microblaze_softmmu_ss.add(files( 'machine.c', )) +microblaze_user_ss = ss.source_set() + target_arch += {'microblaze': microblaze_ss} target_softmmu_arch += {'microblaze': microblaze_softmmu_ss} +target_user_arch += {'microblaze': microblaze_user_ss} diff --git a/target/nios2/meson.build b/target/nios2/meson.build index e643917db1..00367056fa 100644 --- a/target/nios2/meson.build +++ b/target/nios2/meson.build @@ -11,5 +11,8 @@ nios2_ss.add(files( nios2_softmmu_ss = ss.source_set() nios2_softmmu_ss.add(files('monitor.c')) +nios2_user_ss = ss.source_set() + target_arch += {'nios2': nios2_ss} target_softmmu_arch += {'nios2': nios2_softmmu_ss} +target_user_arch += {'nios2': nios2_user_ss} diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build index 9774a58306..794a9e8161 100644 --- a/target/openrisc/meson.build +++ b/target/openrisc/meson.build @@ -19,5 +19,8 @@ openrisc_ss.add(files( openrisc_softmmu_ss = ss.source_set() openrisc_softmmu_ss.add(files('machine.c')) +openrisc_user_ss = ss.source_set() + target_arch += {'openrisc': openrisc_ss} target_softmmu_arch += {'openrisc': openrisc_softmmu_ss} +target_user_arch += {'openrisc': openrisc_user_ss} diff --git a/target/ppc/meson.build b/target/ppc/meson.build index a4f18ff414..0afaea25dd 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -51,5 +51,8 @@ ppc_softmmu_ss.add(when: 'TARGET_PPC64', if_true: files( 'mmu-radix64.c', )) +ppc_user_ss = ss.source_set() + target_arch += {'ppc': ppc_ss} target_softmmu_arch += {'ppc': ppc_softmmu_ss} +target_user_arch += {'ppc': ppc_user_ss} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index af6c3416b7..673b35b175 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -27,5 +27,8 @@ riscv_softmmu_ss.add(files( 'machine.c' )) +riscv_user_ss = ss.source_set() + target_arch += {'riscv': riscv_ss} target_softmmu_arch += {'riscv': riscv_softmmu_ss} +target_user_arch += {'riscv': riscv_user_ss} diff --git a/target/s390x/meson.build b/target/s390x/meson.build index c42eadb7d2..1219f64112 100644 --- a/target/s390x/meson.build +++ b/target/s390x/meson.build @@ -58,5 +58,8 @@ if host_machine.cpu_family() == 's390x' and cc.has_link_argument('-Wl,--s390-pgs if_true: declare_dependency(link_args: ['-Wl,--s390-pgste'])) endif +s390x_user_ss = ss.source_set() + target_arch += {'s390x': s390x_ss} target_softmmu_arch += {'s390x': s390x_softmmu_ss} +target_user_arch += {'s390x': s390x_user_ss} diff --git a/target/sh4/meson.build b/target/sh4/meson.build index 56a57576da..5a05729bc1 100644 --- a/target/sh4/meson.build +++ b/target/sh4/meson.build @@ -10,5 +10,8 @@ sh4_ss.add(files( sh4_softmmu_ss = ss.source_set() sh4_softmmu_ss.add(files('monitor.c')) +sh4_user_ss = ss.source_set() + target_arch += {'sh4': sh4_ss} target_softmmu_arch += {'sh4': sh4_softmmu_ss} +target_user_arch += {'sh4': sh4_user_ss} diff --git a/target/sparc/meson.build b/target/sparc/meson.build index a3638b9503..cc77a77064 100644 --- a/target/sparc/meson.build +++ b/target/sparc/meson.build @@ -19,5 +19,8 @@ sparc_softmmu_ss.add(files( 'monitor.c', )) +sparc_user_ss = ss.source_set() + target_arch += {'sparc': sparc_ss} target_softmmu_arch += {'sparc': sparc_softmmu_ss} +target_user_arch += {'sparc': sparc_user_ss} diff --git a/target/tricore/meson.build b/target/tricore/meson.build index 0ccc829517..7086ae1a22 100644 --- a/target/tricore/meson.build +++ b/target/tricore/meson.build @@ -11,5 +11,8 @@ tricore_ss.add(zlib) tricore_softmmu_ss = ss.source_set() +tricore_user_ss = ss.source_set() + target_arch += {'tricore': tricore_ss} target_softmmu_arch += {'tricore': tricore_softmmu_ss} +target_user_arch += {'tricore': tricore_user_ss} diff --git a/target/xtensa/meson.build b/target/xtensa/meson.build index 7c4efa6c62..ade555ae36 100644 --- a/target/xtensa/meson.build +++ b/target/xtensa/meson.build @@ -23,5 +23,8 @@ xtensa_softmmu_ss.add(files( 'xtensa-semi.c', )) +xtensa_user_ss = ss.source_set() + target_arch += {'xtensa': xtensa_ss} target_softmmu_arch += {'xtensa': xtensa_softmmu_ss} +target_user_arch += {'xtensa': xtensa_user_ss}