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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id s1sm605959pfc.6.2021.05.26.21.14.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 May 2021 21:14:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/11] softfloat: Rename float_flag_output_denormal to float_flag_oflush_denormal Date: Wed, 26 May 2021 21:13:56 -0700 Message-Id: <20210527041405.391567-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210527041405.391567-1-richard.henderson@linaro.org> References: <20210527041405.391567-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, mmorrell@tachyum.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The new name emphasizes that the output denormal has been flushed to zero. Patch created mechanically using: sed -i s,float_flag_output_denormal,float_flag_oflush_denormal,g \ $(git grep -l float_flag_output_denormal) Signed-off-by: Richard Henderson --- include/fpu/softfloat-types.h | 2 +- fpu/softfloat.c | 2 +- target/arm/vfp_helper.c | 2 +- target/i386/tcg/fpu_helper.c | 2 +- target/mips/tcg/msa_helper.c | 2 +- target/rx/op_helper.c | 2 +- target/tricore/fpu_helper.c | 6 +++--- fpu/softfloat-parts.c.inc | 2 +- 8 files changed, 10 insertions(+), 10 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 719b4d2531..e2d70ff556 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -149,7 +149,7 @@ enum { float_flag_underflow = 16, float_flag_inexact = 32, float_flag_iflush_denormal = 64, - float_flag_output_denormal = 128 + float_flag_oflush_denormal = 128 }; /* diff --git a/fpu/softfloat.c b/fpu/softfloat.c index fa3a691a5a..cb077cf111 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -4591,7 +4591,7 @@ floatx80 roundAndPackFloatx80(FloatX80RoundPrec roundingPrecision, bool zSign, } if ( zExp <= 0 ) { if (status->flush_to_zero) { - float_raise(float_flag_output_denormal, status); + float_raise(float_flag_oflush_denormal, status); return packFloatx80(zSign, 0, 0); } isTiny = status->tininess_before_rounding diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 0a43ccc6fa..5864553718 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -46,7 +46,7 @@ static inline int vfp_exceptbits_from_host(int host_bits) if (host_bits & float_flag_overflow) { target_bits |= 4; } - if (host_bits & (float_flag_underflow | float_flag_output_denormal)) { + if (host_bits & (float_flag_underflow | float_flag_oflush_denormal)) { target_bits |= 8; } if (host_bits & float_flag_inexact) { diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index c402daf659..c9779a9fe0 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -3001,7 +3001,7 @@ void update_mxcsr_from_sse_status(CPUX86State *env) (flags & float_flag_overflow ? FPUS_OE : 0) | (flags & float_flag_underflow ? FPUS_UE : 0) | (flags & float_flag_inexact ? FPUS_PE : 0) | - (flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE : + (flags & float_flag_oflush_denormal ? FPUS_UE | FPUS_PE : 0)); } diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 992d348aa3..51791f946b 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -6240,7 +6240,7 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal) } /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */ - if ((ieee_exception_flags & float_flag_output_denormal) && + if ((ieee_exception_flags & float_flag_oflush_denormal) && (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) { mips_exception_flags |= FP_INEXACT; if (action & CLEAR_FS_UNDERFLOW) { diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index eb2c4a41fb..ef904eb5f9 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -98,7 +98,7 @@ static void update_fpsw(CPURXState *env, float32 ret, uintptr_t retaddr) SET_FPSW(X); } if ((xcpt & (float_flag_iflush_denormal - | float_flag_output_denormal)) + | float_flag_oflush_denormal)) && !FIELD_EX32(env->fpsw, FPSW, DN)) { env->fpsw = FIELD_DP32(env->fpsw, FPSW, CE, 1); } diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c index cb7ee7dd35..7c826f9b7b 100644 --- a/target/tricore/fpu_helper.c +++ b/target/tricore/fpu_helper.c @@ -43,7 +43,7 @@ static inline uint8_t f_get_excp_flags(CPUTriCoreState *env) & (float_flag_invalid | float_flag_overflow | float_flag_underflow - | float_flag_output_denormal + | float_flag_oflush_denormal | float_flag_divbyzero | float_flag_inexact); } @@ -99,7 +99,7 @@ static void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags) some_excp = 1; } - if (flags & float_flag_underflow || flags & float_flag_output_denormal) { + if (flags & float_flag_underflow || flags & float_flag_oflush_denormal) { env->FPU_FU = 1 << 31; some_excp = 1; } @@ -109,7 +109,7 @@ static void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags) some_excp = 1; } - if (flags & float_flag_inexact || flags & float_flag_output_denormal) { + if (flags & float_flag_inexact || flags & float_flag_oflush_denormal) { env->PSW |= 1 << 26; some_excp = 1; } diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index be29ba0aa3..72e2b24539 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -227,7 +227,7 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s, } frac_shr(p, frac_shift); } else if (s->flush_to_zero) { - flags |= float_flag_output_denormal; + flags |= float_flag_oflush_denormal; p->cls = float_class_zero; exp = 0; frac_clear(p);