From patchwork Wed May 26 23:47:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 448814 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp33480jac; Wed, 26 May 2021 17:27:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkNtjJSK8SzX70Sh8j7aSHMLc4eTkApQ5KdCanCJjhR3UeuG8h8z7Tn/91fdRLbWxSSip3 X-Received: by 2002:a05:620a:24cf:: with SMTP id m15mr767704qkn.435.1622075274291; Wed, 26 May 2021 17:27:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622075274; cv=none; d=google.com; s=arc-20160816; b=O2uW4+xuVCVOzu7y/5K2q3Tzs7pFhiMIavF+5Uw8L0pQC/xtsZkfnSvSUlSHpdzznJ fdu+EnyFrB8c9bj9nY6PunZjVqCtphA1J5RjWd6MRLEDkrnpaeXrx+mh0w+E+j+2rKFA 9Hl0PA1Q3nqTxQh0Ozu2tinuxbFF+KnnNjzcYyR5dLlS+LmaV1toMr+t2+K7JRP2OhMs vFcaSQzJzhkgYUnW1LUOFcwN9WkeVnwNR1YYbRMGr4L/p/IPmf3DByNeyiO6zGKmA27G Dy1OXfN/bvAMl9zwrrBgRgMIAOoslP52HZMcct6elXYMWqMlNss1ZyJmMhORZGqWwVqp qvbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KggNdH/EFsJ3T1kmCx5Td3eZBoTdhzd36Y4s4qQekSU=; b=QON7d7teEuldtv461GiTxaMXd6J9C9fkJHXdeHcnQLbecGIVgOR6sYbX/Ap6V5Ltwb IgdV58I37Kjs7ytFswSTn0RsVnV2MBYbHB9aRUa6Psugppx+q9nWW7fw1dsQYyc3C9hQ AfcHx+bLrI0v946zZNJIuSTUqTXzsxEdE4MTyY8jtr8/2Cr29FEAkoSXsPymmmpmUxcO QoMwbigDRNCJCC7HMNoReMU+giM8NGWDZzt+rCtZgllcOVySrfSbqjvGDn2KRk5ycUu/ Dr5vu8qTFQJrKb3UWUnOUwzNiXXsLy8uDp1pkp8dMHpkRh3IjBnXOSruTwgnkWtkk+r7 LdPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=arbrUCu7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y8si484978qto.186.2021.05.26.17.27.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 26 May 2021 17:27:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=arbrUCu7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43600 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lm3sP-0005sn-Oy for patch@linaro.org; Wed, 26 May 2021 20:27:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35060) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lm3Ff-00068R-2p for qemu-devel@nongnu.org; Wed, 26 May 2021 19:47:56 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:46774) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lm3FU-0004e6-Ov for qemu-devel@nongnu.org; Wed, 26 May 2021 19:47:50 -0400 Received: by mail-pf1-x431.google.com with SMTP id y15so2194350pfn.13 for ; Wed, 26 May 2021 16:47:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KggNdH/EFsJ3T1kmCx5Td3eZBoTdhzd36Y4s4qQekSU=; b=arbrUCu7Zshk+oAH4EDP9DYGwWaQV9VYDzeVS/oA3sK9I35yEhihDSJ66nG8KRDPyf 9UMICYeDBLbckwpHxFdtOLX2foVeAy60VrM5YGvNc/iVsIv1wqlhWd03OnPDceU/RgS9 r0EcGE5oLVGQLtq2Ud7Z/oKFkqqV6A6PgOAcitt4VSGkxZFYj2agDYk2XCUiAy2N7klj c4EcEBkzAVPdLLntTDn+s7QX2F4Aql/70IPJzi3cJv1FRaM9cVcHjIaEjvxO2/c/2HNQ r9jB2sfLfeEFYnFDpcpSwOsULsuxbgvzxgYGtT8RkDr9PR7mJjWTlwTFgVkrZUAYDitu jbng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KggNdH/EFsJ3T1kmCx5Td3eZBoTdhzd36Y4s4qQekSU=; b=IDu0HBCMnLfjxvvlBq9IF0CYGkvGoK1xV3MgcGCR0BuFe59zGAicms4MYUEz8QI1Vp UDP4JBPFYrzF2O0qU4pRkvCea5vSRJ6barJffhY8a92F4ymo17eiM1wLjwA+QE/mCqIS YsenTnTQYtB1je1XDt2hWLS4SgeJw1U+ppsRYnKbZLuOAxTmnm1q9mlCV7cv8ifdSLIP UHesObKMN12dXt/C0ce1O5aXgi4QAW9B4Y/g8rkPNy9f73kIkW5F/nOyaNFERqbViTzJ LziFycYzAJJLVpZd+TBBeKnUSrVLymmYIE+96W4/CZ9z4Q4Q9+Goo2QpkbqH3w/efk5H LqbA== X-Gm-Message-State: AOAM533LQOt2HoJ26jopHAifnLNHJVNDmU8h4kIOs2BDmbXYlCfPMDCr eoeT7os30VVyoaXniSOKE+G4U5GaJoHkzw== X-Received: by 2002:aa7:9a8e:0:b029:2e7:e3fd:4fa4 with SMTP id w14-20020aa79a8e0000b02902e7e3fd4fa4mr923249pfi.63.1622072856793; Wed, 26 May 2021 16:47:36 -0700 (PDT) Received: from localhost.localdomain (174-21-70-228.tukw.qwest.net. [174.21.70.228]) by smtp.gmail.com with ESMTPSA id g13sm285355pfi.18.2021.05.26.16.47.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 May 2021 16:47:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 30/31] target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed Date: Wed, 26 May 2021 16:47:09 -0700 Message-Id: <20210526234710.125396-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210526234710.125396-1-richard.henderson@linaro.org> References: <20210526234710.125396-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a flag to MIPSCPUClass in order to avoid needing to replace mips_tcg_ops.do_transaction_failed. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-ID: <20210227232519.222663-2-richard.henderson@linaro.org> --- target/mips/cpu-qom.h | 3 +++ hw/mips/jazz.c | 35 +++-------------------------------- target/mips/tcg/op_helper.c | 3 ++- 3 files changed, 8 insertions(+), 33 deletions(-) -- 2.25.1 diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 826ab13019..dda0c911fa 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -47,6 +47,9 @@ struct MIPSCPUClass { DeviceRealize parent_realize; DeviceReset parent_reset; const struct mips_def_t *cpu_def; + + /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */ + bool no_data_aborts; }; diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index dba2088ed1..1e1cf8154e 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -119,30 +119,6 @@ static const MemoryRegionOps dma_dummy_ops = { #define MAGNUM_BIOS_SIZE \ (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) -static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, - uintptr_t retaddr); - -static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, - uintptr_t retaddr) -{ - if (access_type != MMU_INST_FETCH) { - /* ignore invalid access (ie do not raise exception) */ - return; - } - (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type, - mmu_idx, attrs, response, retaddr); -} -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ - static void mips_jazz_init(MachineState *machine, enum jazz_model_e jazz_model) { @@ -151,7 +127,7 @@ static void mips_jazz_init(MachineState *machine, int bios_size, n; Clock *cpuclk; MIPSCPU *cpu; - CPUClass *cc; + MIPSCPUClass *mcc; CPUMIPSState *env; qemu_irq *i8259; rc4030_dma *dmas; @@ -198,8 +174,6 @@ static void mips_jazz_init(MachineState *machine, * However, we can't simply add a global memory region to catch * everything, as this would make all accesses including instruction * accesses be ignored and not raise exceptions. - * So instead we hijack the do_transaction_failed method on the CPU, and - * do not raise exceptions for data access. * * NOTE: this behaviour of raising exceptions for bad instruction * fetches but not bad data accesses was added in commit 54e755588cf1e9 @@ -209,11 +183,8 @@ static void mips_jazz_init(MachineState *machine, * we could replace this hijacking of CPU methods with a simple global * memory region that catches all memory accesses, as we do on Malta. */ - cc = CPU_GET_CLASS(cpu); -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - real_do_transaction_failed = cc->tcg_ops->do_transaction_failed; - cc->tcg_ops->do_transaction_failed = mips_jazz_do_transaction_failed; -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ + mcc = MIPS_CPU_GET_CLASS(cpu); + mcc->no_data_aborts = true; /* allocate RAM */ memory_region_add_subregion(address_space, 0, machine->ram); diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index ce1549c985..fafbf1faca 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -409,11 +409,12 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MemTxResult response, uintptr_t retaddr) { MIPSCPU *cpu = MIPS_CPU(cs); + MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); CPUMIPSState *env = &cpu->env; if (access_type == MMU_INST_FETCH) { do_raise_exception(env, EXCP_IBE, retaddr); - } else { + } else if (!mcc->no_data_aborts) { do_raise_exception(env, EXCP_DBE, retaddr); } }