From patchwork Tue May 25 01:03:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 447143 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp3843781jac; Mon, 24 May 2021 19:06:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwYP2LfgodmSRW9S1pthiDXetvpmm/PczyK2Jl6uOd7EOCHJlyuW8D1696Y/Z68yP0UQVdl X-Received: by 2002:ac8:6a1a:: with SMTP id t26mr9453462qtr.361.1621908399338; Mon, 24 May 2021 19:06:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621908399; cv=none; d=google.com; s=arc-20160816; b=ESELWsNDnxuABfMd+2ObPGaPnJNAGyRavptjiEHzp7GHTLdDQZ7fht+JnxXUbuzNhN pIyOdfrmoGuSzR9y5nRznLblZrUuRg+hFkUkO01Nq9LDvP9xvmyAONu7xVS7+p4WMF/F nR4V4kiIbT3J0zE4EM76dS5Kt+IELN8O/Ijjc8iCSnp//6mMxhVgKxpm88tmvg2PXZfR VdYXPRpIhZnAgzC/RkrMEiuRNdUsqPfqGTkkbt0wJFdI8sZr07fQGm3MSQcIeczDoWbl rMTtdWfpEvTHEQfmEKTOj2lNd+Ufb2D10pKibslPv5E9Yhi1NpwGYqEe3KnOTWnH/iQP AGRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Rjy5u/+r3N9Im1B+TWU6WpNfVMB2c2jYme3uNKhY+Qg=; b=bw51B6CcMVk4+DLIjDqXr1v0cowuKsu3F3S9sDNR2/xg25y3D+9JOewtNWVYaRvUtq KlZ+VBPW/xTpUoyO0XPK1dN8imOGG5bbfgRgZaglnOVaQEj2weltlJYYpsAJHsOt9G6j VVfIgCRwkKZutcxN7DtN18lZq2wNMVZ78zrXnX5M8sAxvJ8keZ0v4We1SaPEazmdRGLY SWu0GewcwcvuTEaal7825ldeJ702wouorJ2IF0OdM4oCqp2eBQRfJbbpourQDzU6VtkY zQiaUCpbtzMYM08/+1Nl9cu21MIgMCCNIdyQuvl56z8Bb52sMO2qZcO1dSUrId21dX1V iBdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MAcDLZ2e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 2si9971145qta.24.2021.05.24.19.06.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 May 2021 19:06:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MAcDLZ2e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50860 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1llMSs-0007fx-KA for patch@linaro.org; Mon, 24 May 2021 22:06:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56430) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1llLb7-0006Jr-TZ for qemu-devel@nongnu.org; Mon, 24 May 2021 21:11:05 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:44005) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1llLax-0005sP-LJ for qemu-devel@nongnu.org; Mon, 24 May 2021 21:11:05 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d78so21408313pfd.10 for ; Mon, 24 May 2021 18:10:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rjy5u/+r3N9Im1B+TWU6WpNfVMB2c2jYme3uNKhY+Qg=; b=MAcDLZ2eyHv/aBb5RLp0f3Tn/QXEh+S/Ct6PqSZKpenOJ9SteNs/Pm1PnLta19SNgE fiPpvjdEMZjEL51Ye7ISmt1CDpQH0WNQrhE5HenvCheHWf1wft89KiSu2SAENhi2Z2yJ DpRSUdQYi/wVe0qS+xLeCXrW6YpatHfN+2ym0s+5NSil2XlXdHFij0nrC5jzp/6QKSLg xH4dVA2Uvm4NPVV580X+RbdxvEIM07e/WPm7Xo94V5HkcaqpxtlhbO1hdLrwPk1qAhS/ kpAsVt5MzI9MXC4WDI6gKf7gkEv+iOUmENYeJYtwcjhrOmqB+FAwug6Hk8LdGMFdrxHI Arpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Rjy5u/+r3N9Im1B+TWU6WpNfVMB2c2jYme3uNKhY+Qg=; b=uGCKnNVkclOHhdEii7Bfhb9Ova2zvo2AttNXb0wnTHiQMDaShFrWENKjsdo7IqcXMa WKNgJfnd5V6XWnT3S4bqB3yq7BiG27mbBLbPLvdzsjzgFSjPS3DTUjQxzmOmHSOFpZWE vU3q8Eq9Nz6+NspGLDaEDIRa4DaW9Tsg+wrThL+QYbULMTasdxzL+FZM55ZzCrCKsQED GtgtK420jDwsL+7vtnA2MITpl6T4t+FSlZQ3efzoXBSfM2CYNqLGi7ingjYJm+JV7BxY H9+oB3i4YYiHVf4Kigcnc703y3IPS1GZpaj06ndswLKOCbDN2B66X9W+8e67rmWQszLt 0sAg== X-Gm-Message-State: AOAM532SxWFuIpU80Eu5BQYMsuI9CjCj1O+lcuWmMuUO6oF7dr2cFT+o jaQeP2hCqmUWsht361ls9NzamBG85dYtKQ== X-Received: by 2002:a63:a549:: with SMTP id r9mr16319196pgu.148.1621905051709; Mon, 24 May 2021 18:10:51 -0700 (PDT) Received: from localhost.localdomain (174-21-70-228.tukw.qwest.net. [174.21.70.228]) by smtp.gmail.com with ESMTPSA id i8sm10614839pjs.54.2021.05.24.18.10.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 May 2021 18:10:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 84/92] target/arm: Split out do_neon_ddda_fpst Date: Mon, 24 May 2021 18:03:50 -0700 Message-Id: <20210525010358.152808-85-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210525010358.152808-1-richard.henderson@linaro.org> References: <20210525010358.152808-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out a helper that can handle the 4-register format for helpers shared with SVE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-neon.c | 98 ++++++++++++++++--------------------- 1 file changed, 43 insertions(+), 55 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 45fa5166f3..1a8fc7fb39 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -151,24 +151,21 @@ static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var) } } -static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) +static bool do_neon_ddda_fpst(DisasContext *s, int q, int vd, int vn, int vm, + int data, ARMFPStatusFlavour fp_flavour, + gen_helper_gvec_4_ptr *fn_gvec_ptr) { - int opr_sz; - TCGv_ptr fpst; - gen_helper_gvec_4_ptr *fn_gvec_ptr; - - if (!dc_isar_feature(aa32_vcma, s) - || (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s))) { - return false; - } - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (((vd | vn | vm) & 0x10) && !dc_isar_feature(aa32_simd_r32, s)) { return false; } - if ((a->vn | a->vm | a->vd) & a->q) { + /* + * UNDEF accesses to odd registers for each bit of Q. + * Q will be 0b111 for all Q-reg instructions, otherwise + * when we have mixed Q- and D-reg inputs. + */ + if (((vd & 1) * 4 | (vn & 1) * 2 | (vm & 1)) & q) { return false; } @@ -176,20 +173,34 @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) return true; } - opr_sz = (1 + a->q) * 8; - fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD); - fn_gvec_ptr = (a->size == MO_16) ? - gen_helper_gvec_fcmlah : gen_helper_gvec_fcmlas; - tcg_gen_gvec_4_ptr(vfp_reg_offset(1, a->vd), - vfp_reg_offset(1, a->vn), - vfp_reg_offset(1, a->vm), - vfp_reg_offset(1, a->vd), - fpst, opr_sz, opr_sz, a->rot, - fn_gvec_ptr); + int opr_sz = q ? 16 : 8; + TCGv_ptr fpst = fpstatus_ptr(fp_flavour); + + tcg_gen_gvec_4_ptr(vfp_reg_offset(1, vd), + vfp_reg_offset(1, vn), + vfp_reg_offset(1, vm), + vfp_reg_offset(1, vd), + fpst, opr_sz, opr_sz, data, fn_gvec_ptr); tcg_temp_free_ptr(fpst); return true; } +static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) +{ + if (!dc_isar_feature(aa32_vcma, s)) { + return false; + } + if (a->size == MO_16) { + if (!dc_isar_feature(aa32_fp16_arith, s)) { + return false; + } + return do_neon_ddda_fpst(s, a->q * 7, a->vd, a->vn, a->vm, a->rot, + FPST_STD_F16, gen_helper_gvec_fcmlah); + } + return do_neon_ddda_fpst(s, a->q * 7, a->vd, a->vn, a->vm, a->rot, + FPST_STD, gen_helper_gvec_fcmlas); +} + static bool trans_VCADD(DisasContext *s, arg_VCADD *a) { int opr_sz; @@ -294,43 +305,20 @@ static bool trans_VFML(DisasContext *s, arg_VFML *a) static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a) { - gen_helper_gvec_4_ptr *fn_gvec_ptr; - int opr_sz; - TCGv_ptr fpst; + int data = (a->index << 2) | a->rot; if (!dc_isar_feature(aa32_vcma, s)) { return false; } - if (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s)) { - return false; + if (a->size == MO_16) { + if (!dc_isar_feature(aa32_fp16_arith, s)) { + return false; + } + return do_neon_ddda_fpst(s, a->q * 6, a->vd, a->vn, a->vm, data, + FPST_STD_F16, gen_helper_gvec_fcmlah_idx); } - - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { - return false; - } - - if ((a->vd | a->vn) & a->q) { - return false; - } - - if (!vfp_access_check(s)) { - return true; - } - - fn_gvec_ptr = (a->size == MO_16) ? - gen_helper_gvec_fcmlah_idx : gen_helper_gvec_fcmlas_idx; - opr_sz = (1 + a->q) * 8; - fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD); - tcg_gen_gvec_4_ptr(vfp_reg_offset(1, a->vd), - vfp_reg_offset(1, a->vn), - vfp_reg_offset(1, a->vm), - vfp_reg_offset(1, a->vd), - fpst, opr_sz, opr_sz, - (a->index << 2) | a->rot, fn_gvec_ptr); - tcg_temp_free_ptr(fpst); - return true; + return do_neon_ddda_fpst(s, a->q * 6, a->vd, a->vn, a->vm, data, + FPST_STD, gen_helper_gvec_fcmlas_idx); } static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)