From patchwork Tue May 25 01:03:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 447133 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp3838865jac; Mon, 24 May 2021 18:59:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxiiZw6PPTnp6ozmWHjdhnpOinTCV83PCQMXyzeHVLSMZh5hHW69EKnv1yXF4dkG+fUKT0O X-Received: by 2002:a5d:8a0a:: with SMTP id w10mr18187124iod.188.1621907978195; Mon, 24 May 2021 18:59:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621907978; cv=none; d=google.com; s=arc-20160816; b=FcCG4jNTqF0TZGUgfsClGxvI27h4AqeyHI6+oy/fL/gdQt4G3h03pnViCwFqBEh9XZ /P0WrCOAZyOtbSO+/guxNwnPvGLrTLNc9+hJDTUDHNpg+Mbe1bsWCupsLTnxRy7eKign nDjyCZrcDWQfVm7qHCb7wIOrewOQGPDmY4LmF472dW6ulsl7aCE+4m69ZplJQG3ARl0z GxC3ySdaHHh0Jo2c/o71vDf46eBHvcRbIv2ESjvXQSTmedHD4ybWugTKXeiao8XAOm4t v/DLvBd3yxfE2jPf5QZP/o0l0I+B8Pe6soPYoDJ+RGNtDH6SLArNQl1ng5Ina26/PToc tJLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xVLmkte3/X8WeOPRHb0OAi+AOLu5ah+uxiTRZR828b8=; b=c0EK52tE0r5xa89qX2Ym+SooxK1+svBjsq9COH19LR4U9mw7Iz1tNrdA2c57TLi5G8 ygqt7UjqKh9iAI1YcLAHegQsMJXe1IDTUj77AsGmyC+PwpbU9m6SiRb+5Ak/F7VusNrV dHHFTcXzM3JX3fCPVpX+bMRdfEGT/qXur1yAQFF5JAN7YPggAHMo5iCfRIIocy7fgdu8 Unwnq1hmnMEVouA0KmHDcKuGYKuipSR06FpcDqS0jVG3M+TbOgvslKeM4wcK+VQQzIfk bPJmjDr0nQScRlKcOv4DKoK1cu/yliv2pQbNXSVm6EFLmSlPMjmMUP3Ofxvz5xIgQBGT LR+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dXsAbzQf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y8si9580023jan.118.2021.05.24.18.59.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 May 2021 18:59:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dXsAbzQf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57986 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1llMM5-00021u-Kj for patch@linaro.org; Mon, 24 May 2021 21:59:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55338) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1llLYH-0008Sv-FR for qemu-devel@nongnu.org; Mon, 24 May 2021 21:08:10 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:40481) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1llLXr-00041I-UJ for qemu-devel@nongnu.org; Mon, 24 May 2021 21:08:09 -0400 Received: by mail-pf1-x430.google.com with SMTP id x188so22273057pfd.7 for ; Mon, 24 May 2021 18:07:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xVLmkte3/X8WeOPRHb0OAi+AOLu5ah+uxiTRZR828b8=; b=dXsAbzQfuSoNAh60M8w9PqGejS9pb7zhvdt32oQ/WPbJWAuhv3VrtNHI+ds1EjpupQ sVJJen/zU1Nc3woOC/mgSFb7LLr331ce1IN7rzJUZg5m3uM9hG2ameTNoy/Nb4O3IhzP d/CbZQ42iQPwI5dK7anIOHGVdIT0BZvShOzfjnSUa1NNRg9jQ6CZT72XLOqbncW2ynHQ F0NTRGcUaDwT1KxLU9f892dqhS2ORHQ6c4OLqgM871RiKuLZQQmZKTR43osmQ7N5pzeO PJerB6ArtyO95t+2pow9mu19ncmMIF2ahKlRO5qn6D0S/03sDCbIN9TK4n+SOZnLkLE/ E9dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xVLmkte3/X8WeOPRHb0OAi+AOLu5ah+uxiTRZR828b8=; b=MGeazf0fqnOKATp4qJxgKZYPeUDCAg6nZHMb/AUcC88wLmyzfvqVodNGTBO7yNB9aj pMfhDY7esX2oPnNIJMeUsptqs6JZq4m8EN4ce9HlspauOWI/g0szaKbrjCl21cen+Tee Tc5ow4dWqkhrj06WQD8fQTYnnEBcq+a/+BFN3+fHxy5vsbdmnXfV/Q9U1ukQyI35AfDk kTzA9Rlp66OsSoLL752tB8uIyRnuN3jcewsU8BUMLcq//dONVOOT0nVwmdn7NZtQDWPy 95nNnVLVVVL8v6L94V7CV7MK+GCMMQy6BsDCJjgU+HwgugfsiGzWPdC07oW0b5FHB4TK UmjA== X-Gm-Message-State: AOAM533+jydKO/cSejoqj4pFivU5UgvoOn6ElWoVJIkKo5SQ9w5R6lhY AYXwjl8Agtyfq6/BynCkUZlLCw3Csri0zA== X-Received: by 2002:a62:2743:0:b029:2d5:897d:7481 with SMTP id n64-20020a6227430000b02902d5897d7481mr27304397pfn.46.1621904847593; Mon, 24 May 2021 18:07:27 -0700 (PDT) Received: from localhost.localdomain (174-21-70-228.tukw.qwest.net. [174.21.70.228]) by smtp.gmail.com with ESMTPSA id b16sm11748176pju.35.2021.05.24.18.07.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 May 2021 18:07:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 45/92] target/arm: Implement SVE2 gather load insns Date: Mon, 24 May 2021 18:03:11 -0700 Message-Id: <20210525010358.152808-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210525010358.152808-1-richard.henderson@linaro.org> References: <20210525010358.152808-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Stephen Long Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Stephen Long Add decoding logic for SVE2 64-bit/32-bit gather non-temporal load insns. 64-bit * LDNT1SB * LDNT1B (vector plus scalar) * LDNT1SH * LDNT1H (vector plus scalar) * LDNT1SW * LDNT1W (vector plus scalar) * LDNT1D (vector plus scalar) 32-bit * LDNT1SB * LDNT1B (vector plus scalar) * LDNT1SH * LDNT1H (vector plus scalar) * LDNT1W (vector plus scalar) Reviewed-by: Peter Maydell Signed-off-by: Stephen Long Message-Id: <20200422152343.12493-1-steplong@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/sve.decode | 11 +++++++++++ target/arm/translate-sve.c | 8 ++++++++ 2 files changed, 19 insertions(+) -- 2.25.1 diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 5cfe6df0d2..c3958bed6a 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1389,6 +1389,17 @@ UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx +### SVE2 Memory Gather Load Group + +# SVE2 64-bit gather non-temporal load +# (scalar plus unpacked 32-bit unscaled offsets) +LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \ + &rprr_gather_load xs=0 esz=3 scale=0 ff=0 + +# SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets) +LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \ + &rprr_gather_load xs=0 esz=2 scale=0 ff=0 + ### SVE2 Memory Store Group # SVE2 64-bit scatter non-temporal store (vector plus scalar) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index ac43bb02be..a64ad04c50 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -6015,6 +6015,14 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) return true; } +static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a) +{ + if (!dc_isar_feature(aa64_sve2, s)) { + return false; + } + return trans_LD1_zprz(s, a); +} + /* Indexed by [mte][be][xs][msz]. */ static gen_helper_gvec_mem_scatter * const scatter_store_fn32[2][2][2][3] = { { /* MTE Inactive */