Message ID | 20210519183050.875453-20-richard.henderson@linaro.org |
---|---|
State | Accepted |
Commit | 0046060e5dc232beb4dc942ec76852841739c109 |
Headers | show
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Series |
target/i386 translate cleanups
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expand
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diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 4222f09b6f..7e296b39f5 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -101,7 +101,6 @@ typedef struct DisasContext { int vex_v; /* vex vvvv register, without 1's complement. */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; - int f_st; /* currently unused */ int tf; /* TF cpu flag */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ @@ -8507,7 +8506,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0)); g_assert(ADDSEG(dc) == ((flags & HF_ADDSEG_MASK) != 0)); - dc->f_st = 0; dc->tf = (flags >> TF_SHIFT) & 1; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false;