diff mbox series

[18/24] target/ppc: Push real-mode handling into ppc_radix64_xlate

Message ID 20210518201146.794854-19-richard.henderson@linaro.org
State Superseded
Headers show
Series target/ppc: Clean up mmu translation | expand

Commit Message

Richard Henderson May 18, 2021, 8:11 p.m. UTC 
This removes some incomplete duplication between
ppc_radix64_handle_mmu_fault and ppc_radix64_get_phys_page_debug.
The former was correct wrt SPR_HRMOR and the latter was not.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/ppc/mmu-radix64.c | 77 ++++++++++++++++++----------------------
 1 file changed, 34 insertions(+), 43 deletions(-)

-- 
2.25.1

Comments

Bruno Piazera Larsen May 19, 2021, 5:44 p.m. UTC | #1 
On 18/05/2021 17:11, Richard Henderson wrote:
> This removes some incomplete duplication between

> ppc_radix64_handle_mmu_fault and ppc_radix64_get_phys_page_debug.

> The former was correct wrt SPR_HRMOR and the latter was not.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Bruno Larsen (billionai)<bruno.larsen@eldorado.org.br>


> ---

>   target/ppc/mmu-radix64.c | 77 ++++++++++++++++++----------------------

>   1 file changed, 34 insertions(+), 43 deletions(-)

>

> diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c

> index f6d96f73b2..76a5cc8cdb 100644

> --- a/target/ppc/mmu-radix64.c

> +++ b/target/ppc/mmu-radix64.c

> @@ -466,7 +466,6 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,

>    */

>   static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr,

>                                MMUAccessType access_type,

> -                             bool relocation,

>                                hwaddr *raddr, int *psizep, int *protp,

>                                bool guest_visible)

>   {

> @@ -475,6 +474,37 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr,

>       ppc_v3_pate_t pate;

>       int psize, prot;

>       hwaddr g_raddr;

> +    bool relocation;

> +

> +    assert(!(msr_hv && cpu->vhyp));

> +

> +    relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr);

> +

> +    /* HV or virtual hypervisor Real Mode Access */

> +    if (!relocation && (msr_hv || cpu->vhyp)) {

> +        /* In real mode top 4 effective addr bits (mostly) ignored */

> +        *raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;

> +

> +        /* In HV mode, add HRMOR if top EA bit is clear */

> +        if (msr_hv || !env->has_hv_mode) {

> +            if (!(eaddr >> 63)) {

> +                *raddr |= env->spr[SPR_HRMOR];

> +           }

> +        }

> +        *protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC;

> +        *psizep = TARGET_PAGE_BITS;

> +        return 0;

> +    }

> +

> +    /*

> +     * Check UPRT (we avoid the check in real mode to deal with

> +     * transitional states during kexec.

> +     */

> +    if (guest_visible && !ppc64_use_proc_tbl(cpu)) {

> +        qemu_log_mask(LOG_GUEST_ERROR,

> +                      "LPCR:UPRT not set in radix mode ! LPCR="

> +                      TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);

> +    }

>   

>       /* Virtual Mode Access - get the fully qualified address */

>       if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pid)) {

> @@ -560,43 +590,11 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,

>                                    MMUAccessType access_type, int mmu_idx)

>   {

>       CPUState *cs = CPU(cpu);

> -    CPUPPCState *env = &cpu->env;

>       int page_size, prot;

> -    bool relocation;

>       hwaddr raddr;

>   

> -    assert(!(msr_hv && cpu->vhyp));

> -

> -    relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr);

> -    /* HV or virtual hypervisor Real Mode Access */

> -    if (!relocation && (msr_hv || cpu->vhyp)) {

> -        /* In real mode top 4 effective addr bits (mostly) ignored */

> -        raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;

> -

> -        /* In HV mode, add HRMOR if top EA bit is clear */

> -        if (msr_hv || !env->has_hv_mode) {

> -            if (!(eaddr >> 63)) {

> -                raddr |= env->spr[SPR_HRMOR];

> -           }

> -        }

> -        tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,

> -                     PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,

> -                     TARGET_PAGE_SIZE);

> -        return 0;

> -    }

> -

> -    /*

> -     * Check UPRT (we avoid the check in real mode to deal with

> -     * transitional states during kexec.

> -     */

> -    if (!ppc64_use_proc_tbl(cpu)) {

> -        qemu_log_mask(LOG_GUEST_ERROR,

> -                      "LPCR:UPRT not set in radix mode ! LPCR="

> -                      TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);

> -    }

> -

>       /* Translate eaddr to raddr (where raddr is addr qemu needs for access) */

> -    if (ppc_radix64_xlate(cpu, eaddr, access_type, relocation, &raddr,

> +    if (ppc_radix64_xlate(cpu, eaddr, access_type, &raddr,

>                             &page_size, &prot, true)) {

>           return 1;

>       }

> @@ -608,18 +606,11 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,

>   

>   hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)

>   {

> -    CPUPPCState *env = &cpu->env;

>       int psize, prot;

>       hwaddr raddr;

>   

> -    /* Handle Real Mode */

> -    if ((msr_dr == 0) && (msr_hv || cpu->vhyp)) {

> -        /* In real mode top 4 effective addr bits (mostly) ignored */

> -        return eaddr & 0x0FFFFFFFFFFFFFFFULL;

> -    }

> -

> -    if (ppc_radix64_xlate(cpu, eaddr, 0, msr_dr, &raddr, &psize,

> -                          &prot, false)) {

> +    if (ppc_radix64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr,

> +                          &psize, &prot, false)) {

>           return -1;

>       }

>   

-- 
Bruno Piazera Larsen
Instituto de Pesquisas ELDORADO 
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
<html>
  <head>
    <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
  </head>
  <body>
    <p><br>
    </p>
    <div class="moz-cite-prefix">On 18/05/2021 17:11, Richard Henderson
      wrote:<br>
    </div>
    <blockquote type="cite"
      cite="mid:20210518201146.794854-19-richard.henderson@linaro.org">
      <pre class="moz-quote-pre" wrap="">This removes some incomplete duplication between
ppc_radix64_handle_mmu_fault and ppc_radix64_get_phys_page_debug.
The former was correct wrt SPR_HRMOR and the latter was not.

Signed-off-by: Richard Henderson <a class="moz-txt-link-rfc2396E" href="mailto:richard.henderson@linaro.org">&lt;richard.henderson@linaro.org&gt;</a></pre>

    </blockquote>
    <pre class="moz-quote-pre" wrap="">Reviewed-by: Bruno Larsen (billionai) <a class="moz-txt-link-rfc2396E" href="mailto:bruno.larsen@eldorado.org.br">&lt;bruno.larsen@eldorado.org.br&gt;</a></pre>
    <blockquote type="cite"
      cite="mid:20210518201146.794854-19-richard.henderson@linaro.org">
      <pre class="moz-quote-pre" wrap="">
---
 target/ppc/mmu-radix64.c | 77 ++++++++++++++++++----------------------
 1 file changed, 34 insertions(+), 43 deletions(-)

diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index f6d96f73b2..76a5cc8cdb 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -466,7 +466,6 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
  */
 static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr,
                              MMUAccessType access_type,
-                             bool relocation,
                              hwaddr *raddr, int *psizep, int *protp,
                              bool guest_visible)
 {
@@ -475,6 +474,37 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr,
     ppc_v3_pate_t pate;
     int psize, prot;
     hwaddr g_raddr;
+    bool relocation;
+
+    assert(!(msr_hv &amp;&amp; cpu-&gt;vhyp));
+
+    relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr);
+
+    /* HV or virtual hypervisor Real Mode Access */
+    if (!relocation &amp;&amp; (msr_hv || cpu-&gt;vhyp)) {
+        /* In real mode top 4 effective addr bits (mostly) ignored */
+        *raddr = eaddr &amp; 0x0FFFFFFFFFFFFFFFULL;
+
+        /* In HV mode, add HRMOR if top EA bit is clear */
+        if (msr_hv || !env-&gt;has_hv_mode) {
+            if (!(eaddr &gt;&gt; 63)) {
+                *raddr |= env-&gt;spr[SPR_HRMOR];
+           }
+        }
+        *protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+        *psizep = TARGET_PAGE_BITS;
+        return 0;
+    }
+
+    /*
+     * Check UPRT (we avoid the check in real mode to deal with
+     * transitional states during kexec.
+     */
+    if (guest_visible &amp;&amp; !ppc64_use_proc_tbl(cpu)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "LPCR:UPRT not set in radix mode ! LPCR="
+                      TARGET_FMT_lx "\n", env-&gt;spr[SPR_LPCR]);
+    }
 
     /* Virtual Mode Access - get the fully qualified address */
     if (!ppc_radix64_get_fully_qualified_addr(&amp;cpu-&gt;env, eaddr, &amp;lpid, &amp;pid)) {
@@ -560,43 +590,11 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
                                  MMUAccessType access_type, int mmu_idx)
 {
     CPUState *cs = CPU(cpu);
-    CPUPPCState *env = &amp;cpu-&gt;env;
     int page_size, prot;
-    bool relocation;
     hwaddr raddr;
 
-    assert(!(msr_hv &amp;&amp; cpu-&gt;vhyp));
-
-    relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr);
-    /* HV or virtual hypervisor Real Mode Access */
-    if (!relocation &amp;&amp; (msr_hv || cpu-&gt;vhyp)) {
-        /* In real mode top 4 effective addr bits (mostly) ignored */
-        raddr = eaddr &amp; 0x0FFFFFFFFFFFFFFFULL;
-
-        /* In HV mode, add HRMOR if top EA bit is clear */
-        if (msr_hv || !env-&gt;has_hv_mode) {
-            if (!(eaddr &gt;&gt; 63)) {
-                raddr |= env-&gt;spr[SPR_HRMOR];
-           }
-        }
-        tlb_set_page(cs, eaddr &amp; TARGET_PAGE_MASK, raddr &amp; TARGET_PAGE_MASK,
-                     PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
-                     TARGET_PAGE_SIZE);
-        return 0;
-    }
-
-    /*
-     * Check UPRT (we avoid the check in real mode to deal with
-     * transitional states during kexec.
-     */
-    if (!ppc64_use_proc_tbl(cpu)) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "LPCR:UPRT not set in radix mode ! LPCR="
-                      TARGET_FMT_lx "\n", env-&gt;spr[SPR_LPCR]);
-    }
-
     /* Translate eaddr to raddr (where raddr is addr qemu needs for access) */
-    if (ppc_radix64_xlate(cpu, eaddr, access_type, relocation, &amp;raddr,
+    if (ppc_radix64_xlate(cpu, eaddr, access_type, &amp;raddr,
                           &amp;page_size, &amp;prot, true)) {
         return 1;
     }
@@ -608,18 +606,11 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
 
 hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
 {
-    CPUPPCState *env = &amp;cpu-&gt;env;
     int psize, prot;
     hwaddr raddr;
 
-    /* Handle Real Mode */
-    if ((msr_dr == 0) &amp;&amp; (msr_hv || cpu-&gt;vhyp)) {
-        /* In real mode top 4 effective addr bits (mostly) ignored */
-        return eaddr &amp; 0x0FFFFFFFFFFFFFFFULL;
-    }
-
-    if (ppc_radix64_xlate(cpu, eaddr, 0, msr_dr, &amp;raddr, &amp;psize,
-                          &amp;prot, false)) {
+    if (ppc_radix64_xlate(cpu, eaddr, MMU_DATA_LOAD, &amp;raddr,
+                          &amp;psize, &amp;prot, false)) {
         return -1;
     }
 
</pre>
    </blockquote>
    <div class="moz-signature">-- <br>
      Bruno Piazera Larsen<br>
      <a
href="https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&amp;utm_medium=email&amp;utm_source=RD+Station">Instituto
        de Pesquisas ELDORADO</a><br>
      Departamento Computação Embarcada<br>
      Analista de Software Trainee<br>
      <a href="https://www.eldorado.org.br/disclaimer.html">Aviso Legal
        - Disclaimer</a></div>
  </body>
</html>
diff mbox series

Patch

diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index f6d96f73b2..76a5cc8cdb 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -466,7 +466,6 @@  static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
  */
 static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr,
                              MMUAccessType access_type,
-                             bool relocation,
                              hwaddr *raddr, int *psizep, int *protp,
                              bool guest_visible)
 {
@@ -475,6 +474,37 @@  static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr,
     ppc_v3_pate_t pate;
     int psize, prot;
     hwaddr g_raddr;
+    bool relocation;
+
+    assert(!(msr_hv && cpu->vhyp));
+
+    relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr);
+
+    /* HV or virtual hypervisor Real Mode Access */
+    if (!relocation && (msr_hv || cpu->vhyp)) {
+        /* In real mode top 4 effective addr bits (mostly) ignored */
+        *raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
+
+        /* In HV mode, add HRMOR if top EA bit is clear */
+        if (msr_hv || !env->has_hv_mode) {
+            if (!(eaddr >> 63)) {
+                *raddr |= env->spr[SPR_HRMOR];
+           }
+        }
+        *protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+        *psizep = TARGET_PAGE_BITS;
+        return 0;
+    }
+
+    /*
+     * Check UPRT (we avoid the check in real mode to deal with
+     * transitional states during kexec.
+     */
+    if (guest_visible && !ppc64_use_proc_tbl(cpu)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "LPCR:UPRT not set in radix mode ! LPCR="
+                      TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
+    }
 
     /* Virtual Mode Access - get the fully qualified address */
     if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pid)) {
@@ -560,43 +590,11 @@  int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
                                  MMUAccessType access_type, int mmu_idx)
 {
     CPUState *cs = CPU(cpu);
-    CPUPPCState *env = &cpu->env;
     int page_size, prot;
-    bool relocation;
     hwaddr raddr;
 
-    assert(!(msr_hv && cpu->vhyp));
-
-    relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr);
-    /* HV or virtual hypervisor Real Mode Access */
-    if (!relocation && (msr_hv || cpu->vhyp)) {
-        /* In real mode top 4 effective addr bits (mostly) ignored */
-        raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
-
-        /* In HV mode, add HRMOR if top EA bit is clear */
-        if (msr_hv || !env->has_hv_mode) {
-            if (!(eaddr >> 63)) {
-                raddr |= env->spr[SPR_HRMOR];
-           }
-        }
-        tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
-                     PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
-                     TARGET_PAGE_SIZE);
-        return 0;
-    }
-
-    /*
-     * Check UPRT (we avoid the check in real mode to deal with
-     * transitional states during kexec.
-     */
-    if (!ppc64_use_proc_tbl(cpu)) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "LPCR:UPRT not set in radix mode ! LPCR="
-                      TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
-    }
-
     /* Translate eaddr to raddr (where raddr is addr qemu needs for access) */
-    if (ppc_radix64_xlate(cpu, eaddr, access_type, relocation, &raddr,
+    if (ppc_radix64_xlate(cpu, eaddr, access_type, &raddr,
                           &page_size, &prot, true)) {
         return 1;
     }
@@ -608,18 +606,11 @@  int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
 
 hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
 {
-    CPUPPCState *env = &cpu->env;
     int psize, prot;
     hwaddr raddr;
 
-    /* Handle Real Mode */
-    if ((msr_dr == 0) && (msr_hv || cpu->vhyp)) {
-        /* In real mode top 4 effective addr bits (mostly) ignored */
-        return eaddr & 0x0FFFFFFFFFFFFFFFULL;
-    }
-
-    if (ppc_radix64_xlate(cpu, eaddr, 0, msr_dr, &raddr, &psize,
-                          &prot, false)) {
+    if (ppc_radix64_xlate(cpu, eaddr, MMU_DATA_LOAD, &raddr,
+                          &psize, &prot, false)) {
         return -1;
     }