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[189.204.200.163]) by smtp.gmail.com with ESMTPSA id s5sm8500553qkg.88.2021.05.16.05.34.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 May 2021 05:34:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 28/46] softfloat: Move return_nan to softfloat-parts.c.inc Date: Sun, 16 May 2021 07:34:13 -0500 Message-Id: <20210516123431.718318-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210516123431.718318-1-richard.henderson@linaro.org> References: <20210516123431.718318-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::735; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x735.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, David Hildenbrand Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the same time, convert to pointers, rename to return_nan$N and define a macro for return_nan using QEMU_GENERIC. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- fpu/softfloat.c | 45 ++++++++++++++++++++++----------------- fpu/softfloat-parts.c.inc | 37 ++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 20 deletions(-) create mode 100644 fpu/softfloat-parts.c.inc -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 08fd812ea0..bdc3125e5c 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -709,6 +709,10 @@ static float128 float128_pack_raw(const FloatParts128 *p) #define parts_default_nan(P, S) PARTS_GENERIC_64_128(default_nan, P)(P, S) #define parts_silence_nan(P, S) PARTS_GENERIC_64_128(silence_nan, P)(P, S) +static void parts64_return_nan(FloatParts64 *a, float_status *s); +static void parts128_return_nan(FloatParts128 *a, float_status *s); + +#define parts_return_nan(P, S) PARTS_GENERIC_64_128(return_nan, P)(P, S) /* * Helper functions for softfloat-parts.c.inc, per-size operations. @@ -915,22 +919,6 @@ static FloatParts64 round_canonical(FloatParts64 p, float_status *s, return p; } -static FloatParts64 return_nan(FloatParts64 a, float_status *s) -{ - g_assert(is_nan(a.cls)); - if (is_snan(a.cls)) { - float_raise(float_flag_invalid, s); - if (!s->default_nan_mode) { - parts_silence_nan(&a, s); - return a; - } - } else if (!s->default_nan_mode) { - return a; - } - parts_default_nan(&a, s); - return a; -} - static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status *s) { if (is_snan(a.cls) || is_snan(b.cls)) { @@ -992,6 +980,21 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatParts64 return a; } +#define partsN(NAME) parts64_##NAME +#define FloatPartsN FloatParts64 + +#include "softfloat-parts.c.inc" + +#undef partsN +#undef FloatPartsN +#define partsN(NAME) parts128_##NAME +#define FloatPartsN FloatParts128 + +#include "softfloat-parts.c.inc" + +#undef partsN +#undef FloatPartsN + /* * Pack/unpack routines with a specific FloatFmt. */ @@ -2066,7 +2069,7 @@ static FloatParts64 float_to_float(FloatParts64 a, const FloatFmt *dstf, break; } } else if (is_nan(a.cls)) { - return return_nan(a, s); + parts_return_nan(&a, s); } return a; } @@ -2195,7 +2198,8 @@ static FloatParts64 round_to_int(FloatParts64 a, FloatRoundMode rmode, switch (a.cls) { case float_class_qnan: case float_class_snan: - return return_nan(a, s); + parts_return_nan(&a, s); + break; case float_class_zero: case float_class_inf: @@ -3591,7 +3595,7 @@ FloatRelation bfloat16_compare_quiet(bfloat16 a, bfloat16 b, float_status *s) static FloatParts64 scalbn_decomposed(FloatParts64 a, int n, float_status *s) { if (unlikely(is_nan(a.cls))) { - return return_nan(a, s); + parts_return_nan(&a, s); } if (a.cls == float_class_normal) { /* The largest float type (even though not supported by FloatParts64) @@ -3659,7 +3663,8 @@ static FloatParts64 sqrt_float(FloatParts64 a, float_status *s, const FloatFmt * int bit, last_bit; if (is_nan(a.cls)) { - return return_nan(a, s); + parts_return_nan(&a, s); + return a; } if (a.cls == float_class_zero) { return a; /* sqrt(+-0) = +-0 */ diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc new file mode 100644 index 0000000000..2a3075d6fe --- /dev/null +++ b/fpu/softfloat-parts.c.inc @@ -0,0 +1,37 @@ +/* + * QEMU float support + * + * The code in this source file is derived from release 2a of the SoftFloat + * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and + * some later contributions) are provided under that license, as detailed below. + * It has subsequently been modified by contributors to the QEMU Project, + * so some portions are provided under: + * the SoftFloat-2a license + * the BSD license + * GPL-v2-or-later + * + * Any future contributions to this file after December 1st 2014 will be + * taken to be licensed under the Softfloat-2a license unless specifically + * indicated otherwise. + */ + +static void partsN(return_nan)(FloatPartsN *a, float_status *s) +{ + switch (a->cls) { + case float_class_snan: + float_raise(float_flag_invalid, s); + if (s->default_nan_mode) { + parts_default_nan(a, s); + } else { + parts_silence_nan(a, s); + } + break; + case float_class_qnan: + if (s->default_nan_mode) { + parts_default_nan(a, s); + } + break; + default: + g_assert_not_reached(); + } +}