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[189.204.200.163]) by smtp.gmail.com with ESMTPSA id s5sm8500553qkg.88.2021.05.16.05.34.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 May 2021 05:34:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 17/46] softfloat: Use pointers with parts_default_nan Date: Sun, 16 May 2021 07:34:02 -0500 Message-Id: <20210516123431.718318-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210516123431.718318-1-richard.henderson@linaro.org> References: <20210516123431.718318-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82c; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, David Hildenbrand Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the same time, rename to parts64_default_nan and add a macro for parts_default_nan. This will be flushed out once 128-bit support is added. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- fpu/softfloat.c | 47 +++++++++++++++++++++++----------- fpu/softfloat-specialize.c.inc | 4 +-- 2 files changed, 34 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 398a068b58..c7f95961cf 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -650,6 +650,8 @@ static inline float64 float64_pack_raw(FloatParts64 p) *----------------------------------------------------------------------------*/ #include "softfloat-specialize.c.inc" +#define parts_default_nan parts64_default_nan + /* Canonicalize EXP and FRAC, setting CLS. */ static FloatParts64 sf_canonicalize(FloatParts64 part, const FloatFmt *parm, float_status *status) @@ -848,7 +850,8 @@ static FloatParts64 return_nan(FloatParts64 a, float_status *s) } else if (!s->default_nan_mode) { return a; } - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status *s) @@ -858,7 +861,7 @@ static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status *s) } if (s->default_nan_mode) { - return parts_default_nan(s); + parts_default_nan(&a, s); } else { if (pickNaN(a.cls, b.cls, a.frac > b.frac || @@ -900,7 +903,8 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatParts64 a = c; break; case 3: - return parts_default_nan(s); + parts_default_nan(&a, s); + break; default: g_assert_not_reached(); } @@ -1011,7 +1015,7 @@ static FloatParts64 addsub_floats(FloatParts64 a, FloatParts64 b, bool subtract, if (a.cls == float_class_inf) { if (b.cls == float_class_inf) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); } return a; } @@ -1254,7 +1258,8 @@ static FloatParts64 mul_floats(FloatParts64 a, FloatParts64 b, float_status *s) if ((a.cls == float_class_inf && b.cls == float_class_zero) || (a.cls == float_class_zero && b.cls == float_class_inf)) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } /* Multiply by 0 or Inf */ if (a.cls == float_class_inf || a.cls == float_class_zero) { @@ -1372,7 +1377,8 @@ static FloatParts64 muladd_floats(FloatParts64 a, FloatParts64 b, FloatParts64 c if (inf_zero) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } if (flags & float_muladd_negate_c) { @@ -1396,11 +1402,11 @@ static FloatParts64 muladd_floats(FloatParts64 a, FloatParts64 b, FloatParts64 c if (c.cls == float_class_inf) { if (p_class == float_class_inf && p_sign != c.sign) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&c, s); } else { c.sign ^= sign_flip; - return c; } + return c; } if (p_class == float_class_inf) { @@ -1764,7 +1770,8 @@ static FloatParts64 div_floats(FloatParts64 a, FloatParts64 b, float_status *s) && (a.cls == float_class_inf || a.cls == float_class_zero)) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } /* Inf / x or 0 / x */ if (a.cls == float_class_inf || a.cls == float_class_zero) { @@ -3438,7 +3445,8 @@ static FloatParts64 sqrt_float(FloatParts64 a, float_status *s, const FloatFmt * } if (a.sign) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } if (a.cls == float_class_inf) { return a; /* sqrt(+inf) = +inf */ @@ -3573,30 +3581,37 @@ bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float_status *status) float16 float16_default_nan(float_status *status) { - FloatParts64 p = parts_default_nan(status); + FloatParts64 p; + + parts_default_nan(&p, status); p.frac >>= float16_params.frac_shift; return float16_pack_raw(p); } float32 float32_default_nan(float_status *status) { - FloatParts64 p = parts_default_nan(status); + FloatParts64 p; + + parts_default_nan(&p, status); p.frac >>= float32_params.frac_shift; return float32_pack_raw(p); } float64 float64_default_nan(float_status *status) { - FloatParts64 p = parts_default_nan(status); + FloatParts64 p; + + parts_default_nan(&p, status); p.frac >>= float64_params.frac_shift; return float64_pack_raw(p); } float128 float128_default_nan(float_status *status) { - FloatParts64 p = parts_default_nan(status); + FloatParts64 p; float128 r; + parts_default_nan(&p, status); /* Extrapolate from the choices made by parts_default_nan to fill * in the quad-floating format. If the low bit is set, assume we * want to set all non-snan bits. @@ -3611,7 +3626,9 @@ float128 float128_default_nan(float_status *status) bfloat16 bfloat16_default_nan(float_status *status) { - FloatParts64 p = parts_default_nan(status); + FloatParts64 p; + + parts_default_nan(&p, status); p.frac >>= bfloat16_params.frac_shift; return bfloat16_pack_raw(p); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index bb928b0b9f..47c3652d63 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -129,7 +129,7 @@ static bool parts_is_snan_frac(uint64_t frac, float_status *status) | The pattern for a default generated deconstructed floating-point NaN. *----------------------------------------------------------------------------*/ -static FloatParts64 parts_default_nan(float_status *status) +static void parts64_default_nan(FloatParts64 *p, float_status *status) { bool sign = 0; uint64_t frac; @@ -163,7 +163,7 @@ static FloatParts64 parts_default_nan(float_status *status) } #endif - return (FloatParts64) { + *p = (FloatParts64) { .cls = float_class_qnan, .sign = sign, .exp = INT_MAX,