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[189.204.200.163]) by smtp.gmail.com with ESMTPSA id u6sm4778966qkj.117.2021.05.14.08.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 May 2021 08:14:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 28/50] target/i386: Reorder DisasContext members Date: Fri, 14 May 2021 10:13:20 -0500 Message-Id: <20210514151342.384376-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210514151342.384376-1-richard.henderson@linaro.org> References: <20210514151342.384376-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::836; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x836.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, f4bug@amsat.org, ehabkost@redhat.com, cfontana@suse.de Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Sort all of the single-byte members to the same area of the structure, eliminating 8 bytes of padding. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) -- 2.25.1 Reviewed-by: Paolo Bonzini diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index d48c0f82a9..18f1c0342f 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -76,20 +76,24 @@ static TCGv_i64 cpu_bndu[4]; typedef struct DisasContext { DisasContextBase base; - /* current insn context */ - int8_t override; /* -1 if no override, else R_CS, R_DS, etc */ - uint8_t prefix; + target_ulong pc; /* pc = eip + cs_base */ + target_ulong pc_start; /* pc at TB entry */ + target_ulong cs_base; /* base of CS segment */ + MemOp aflag; MemOp dflag; - target_ulong pc_start; - target_ulong pc; /* pc = eip + cs_base */ - /* current block context */ - target_ulong cs_base; /* base of CS segment */ + + int8_t override; /* -1 if no override, else R_CS, R_DS, etc */ + uint8_t prefix; #ifndef CONFIG_USER_ONLY uint8_t cpl; /* code priv level */ uint8_t iopl; /* i/o priv level */ #endif + uint8_t vex_l; /* vex vector length */ + uint8_t vex_v; /* vex vvvv register, without 1's complement. */ + uint8_t popl_esp_hack; /* for correct popl with esp base handling */ + uint8_t rip_offset; /* only used in x86_64, but left for simplicity */ #ifdef TARGET_X86_64 uint8_t rex_r; @@ -97,16 +101,13 @@ typedef struct DisasContext { uint8_t rex_b; bool rex_w; #endif - uint8_t vex_l; /* vex vector length */ - uint8_t vex_v; /* vex vvvv register, without 1's complement. */ - CCOp cc_op; /* current CC operation */ - bool cc_op_dirty; bool jmp_opt; /* use direct block chaining for direct jumps */ bool repz_opt; /* optimize jumps within repz instructions */ + bool cc_op_dirty; + + CCOp cc_op; /* current CC operation */ int mem_index; /* select memory access functions */ uint32_t flags; /* all execution flags */ - uint8_t popl_esp_hack; /* for correct popl with esp base handling */ - uint8_t rip_offset; /* only used in x86_64, but left for simplicity */ int cpuid_features; int cpuid_ext_features; int cpuid_ext2_features;