Message ID | 20210514151342.384376-24-richard.henderson@linaro.org |
---|---|
State | Superseded |
Headers | show |
Series | target/i386 translate cleanups | expand |
On 14/05/21 17:13, Richard Henderson wrote: > Currently, vex_l is either {0,1}; if in the future we implement > AVX-512, the max value will be 2. In vex_v we store a register > number. This is 0-15 for SSE, and 0-31 for AVX-512. > > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/i386/tcg/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c > index 61c0573c2f..1367e53e4e 100644 > --- a/target/i386/tcg/translate.c > +++ b/target/i386/tcg/translate.c > @@ -97,8 +97,8 @@ typedef struct DisasContext { > uint8_t rex_b; > bool rex_w; > #endif > - int vex_l; /* vex vector length */ > - int vex_v; /* vex vvvv register, without 1's complement. */ > + uint8_t vex_l; /* vex vector length */ > + uint8_t vex_v; /* vex vvvv register, without 1's complement. */ > CCOp cc_op; /* current CC operation */ > bool cc_op_dirty; > int tf; /* TF cpu flag */ > Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 61c0573c2f..1367e53e4e 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -97,8 +97,8 @@ typedef struct DisasContext { uint8_t rex_b; bool rex_w; #endif - int vex_l; /* vex vector length */ - int vex_v; /* vex vvvv register, without 1's complement. */ + uint8_t vex_l; /* vex vector length */ + uint8_t vex_v; /* vex vvvv register, without 1's complement. */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; int tf; /* TF cpu flag */