diff mbox series

[v6,82/82] target/arm: Enable SVE2 and related extensions

Message ID 20210430202610.1136687-83-richard.henderson@linaro.org
State New
Headers show
Series target/arm: Implement SVE2 | expand

Commit Message

Richard Henderson April 30, 2021, 8:26 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/cpu.c   |  1 +
 target/arm/cpu64.c | 13 +++++++++++++
 2 files changed, 14 insertions(+)

-- 
2.25.1

Comments

Peter Maydell May 13, 2021, 7:35 p.m. UTC | #1 
On Fri, 30 Apr 2021 at 22:37, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/arm/cpu.c   |  1 +

>  target/arm/cpu64.c | 13 +++++++++++++

>  2 files changed, 14 insertions(+)

>

> diff --git a/target/arm/cpu.c b/target/arm/cpu.c

> index 0dd623e590..30fd5d5ff7 100644

> --- a/target/arm/cpu.c

> +++ b/target/arm/cpu.c

> @@ -1464,6 +1464,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

>

>          u = cpu->isar.id_isar6;

>          u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);

> +        u = FIELD_DP32(u, ID_ISAR6, I8MM, 0);

>          cpu->isar.id_isar6 = u;

>

>          u = cpu->isar.mvfr0;

> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

> index f0a9e968c9..379f90fab8 100644

> --- a/target/arm/cpu64.c

> +++ b/target/arm/cpu64.c

> @@ -662,6 +662,7 @@ static void aarch64_max_initfn(Object *obj)

>          t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);

>          t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);

>          t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */

> +        t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);

>          cpu->isar.id_aa64isar1 = t;

>

>          t = cpu->isar.id_aa64pfr0;

> @@ -702,6 +703,17 @@ static void aarch64_max_initfn(Object *obj)

>          t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */

>          cpu->isar.id_aa64mmfr2 = t;

>

> +        t = cpu->isar.id_aa64zfr0;

> +        t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);

> +        t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);  /* PMULL */

> +        t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);

> +        t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);

> +        t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);

> +        t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);

> +        t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);

> +        t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);

> +        cpu->isar.id_aa64zfr0 = t;

> +

>          /* Replicate the same data to the 32-bit id registers.  */

>          u = cpu->isar.id_isar5;

>          u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */

> @@ -718,6 +730,7 @@ static void aarch64_max_initfn(Object *obj)

>          u = FIELD_DP32(u, ID_ISAR6, FHM, 1);

>          u = FIELD_DP32(u, ID_ISAR6, SB, 1);

>          u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);

> +        u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);

>          cpu->isar.id_isar6 = u;

>

>          u = cpu->isar.id_pfr0;


Do we need to clear any of these in the "user set has_neon and/or
has_vfp to false" code in arm_cpu_realizefn() ?

thanks
-- PMM
Richard Henderson May 14, 2021, 5:21 p.m. UTC | #2 
On 5/13/21 2:35 PM, Peter Maydell wrote:
> On Fri, 30 Apr 2021 at 22:37, Richard Henderson

> <richard.henderson@linaro.org> wrote:

>>

>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

>> ---

>>   target/arm/cpu.c   |  1 +

>>   target/arm/cpu64.c | 13 +++++++++++++

>>   2 files changed, 14 insertions(+)

>>

>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c

>> index 0dd623e590..30fd5d5ff7 100644

>> --- a/target/arm/cpu.c

>> +++ b/target/arm/cpu.c

>> @@ -1464,6 +1464,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

>>

>>           u = cpu->isar.id_isar6;

>>           u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);

>> +        u = FIELD_DP32(u, ID_ISAR6, I8MM, 0);

>>           cpu->isar.id_isar6 = u;

>>

>>           u = cpu->isar.mvfr0;

>> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

>> index f0a9e968c9..379f90fab8 100644

>> --- a/target/arm/cpu64.c

>> +++ b/target/arm/cpu64.c

>> @@ -662,6 +662,7 @@ static void aarch64_max_initfn(Object *obj)

>>           t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);

>>           t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);

>>           t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */

>> +        t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);

>>           cpu->isar.id_aa64isar1 = t;

>>

>>           t = cpu->isar.id_aa64pfr0;

>> @@ -702,6 +703,17 @@ static void aarch64_max_initfn(Object *obj)

>>           t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */

>>           cpu->isar.id_aa64mmfr2 = t;

>>

>> +        t = cpu->isar.id_aa64zfr0;

>> +        t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);

>> +        t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);  /* PMULL */

>> +        t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);

>> +        t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);

>> +        t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);

>> +        t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);

>> +        t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);

>> +        t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);

>> +        cpu->isar.id_aa64zfr0 = t;

>> +

>>           /* Replicate the same data to the 32-bit id registers.  */

>>           u = cpu->isar.id_isar5;

>>           u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */

>> @@ -718,6 +730,7 @@ static void aarch64_max_initfn(Object *obj)

>>           u = FIELD_DP32(u, ID_ISAR6, FHM, 1);

>>           u = FIELD_DP32(u, ID_ISAR6, SB, 1);

>>           u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);

>> +        u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);

>>           cpu->isar.id_isar6 = u;

>>

>>           u = cpu->isar.id_pfr0;

> 

> Do we need to clear any of these in the "user set has_neon and/or

> has_vfp to false" code in arm_cpu_realizefn() ?


Oh, hmm, yes.  Indeed, I guess we need to disable SVE as well?

I also see that ID_ISAR6.I8MM is currently handled by !has_vfp, but it's really 
an AdvSIMD aka has_neon feature.


r~
diff mbox series

Patch

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0dd623e590..30fd5d5ff7 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1464,6 +1464,7 @@  static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 
         u = cpu->isar.id_isar6;
         u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
+        u = FIELD_DP32(u, ID_ISAR6, I8MM, 0);
         cpu->isar.id_isar6 = u;
 
         u = cpu->isar.mvfr0;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f0a9e968c9..379f90fab8 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -662,6 +662,7 @@  static void aarch64_max_initfn(Object *obj)
         t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
         t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
         t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
+        t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
         cpu->isar.id_aa64isar1 = t;
 
         t = cpu->isar.id_aa64pfr0;
@@ -702,6 +703,17 @@  static void aarch64_max_initfn(Object *obj)
         t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
         cpu->isar.id_aa64mmfr2 = t;
 
+        t = cpu->isar.id_aa64zfr0;
+        t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
+        t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);  /* PMULL */
+        t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
+        t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
+        t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
+        t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
+        t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
+        t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
+        cpu->isar.id_aa64zfr0 = t;
+
         /* Replicate the same data to the 32-bit id registers.  */
         u = cpu->isar.id_isar5;
         u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
@@ -718,6 +730,7 @@  static void aarch64_max_initfn(Object *obj)
         u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
         u = FIELD_DP32(u, ID_ISAR6, SB, 1);
         u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
+        u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
         cpu->isar.id_isar6 = u;
 
         u = cpu->isar.id_pfr0;