| Message ID | 20210427171649.364699-10-luis.pires@eldorado.org.br |
|---|---|
| State | New |
| Headers | show |
| Series | None | expand |
On 27/04/2021 14:16, Luis Pires wrote: > From: Richard Henderson <richard.henderson@linaro.org> > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/ppc/insn32.decode | 8 +++++ > target/ppc/insn64.decode | 14 ++++++++ > target/ppc/translate.c | 29 --------------- > target/ppc/translate/fixedpoint-impl.c.inc | 42 ++++++++++++++++++++++ > 4 files changed, 64 insertions(+), 29 deletions(-) > > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index b175441209..878d2f2f66 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -16,3 +16,11 @@ > # You should have received a copy of the GNU Lesser General Public > # License along with this library; if not, see <http://www.gnu.org/licenses/>. > # > + > +&D rt ra si > +@D ...... rt:5 ra:5 si:s16 &D > + > +### Fixed-Point Arithmetic Instructions > + > +ADDI 001110 ..... ..... ................ @D > +ADDIS 001111 ..... ..... ................ @D > diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode > index 9fc45d0614..68ed2cbff8 100644 > --- a/target/ppc/insn64.decode > +++ b/target/ppc/insn64.decode > @@ -16,3 +16,17 @@ > # You should have received a copy of the GNU Lesser General Public > # License along with this library; if not, see <http://www.gnu.org/licenses/>. > # > + > +# Format MLS:D and 8LS:D > +&PLS_D rt ra si r > + > +%pls_si 32:s18 0:16 > + > +@PLS_D ...... .. ... r:1 .. .................. \ > + ...... rt:5 ra:5 ................ \ > + &PLS_D si=%pls_si > + > +### Fixed-Point Arithmetic Instructions > + > +PADDI 000001 10 0--.-- .................. \ > + 001110 ..... ..... ................ @PLS_D <snip> > + > +static bool trans_ADDI(DisasContext *ctx, arg_D *a) > +{ > + if (a->ra) { > + tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si); > + } else { > + tcg_gen_movi_tl(cpu_gpr[a->rt], a->si); > + } > + return true; > +} > + > +static bool trans_ADDIS(DisasContext *ctx, arg_D *a) > +{ > + a->si <<= 16; > + return trans_ADDI(ctx, a); > +} > + > +static bool trans_PADDI(DisasContext *ctx, arg_PLS_D *a) > +{ > + if (!resolve_PLS_D(ctx, a)) { > + return false; > + } > + if (a->ra) { > + tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si); > + } else { > + tcg_gen_movi_tl(cpu_gpr[a->rt], a->si); > + } > + return true; > +} > In our first attempt, we did some efforts to keep prefixed instructions type 0b10 and 0b11 under the same implementation as their word-size counterpart, i.e. trans_ADDI and trans_PADDI had the same signature and just forwarded their arguments to a third method that does the real work. Is this kind of approach desirable? We initially achieved this by using const_elt to set r=0 for addi, which is not particularly nice, but we can look for other solutions. Thanks, Matheus K. Ferst Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/> Analista de Software Júnior Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
On 4/28/21 7:10 AM, Matheus K. Ferst wrote: > In our first attempt, we did some efforts to keep prefixed instructions type > 0b10 and 0b11 under the same implementation as their word-size counterpart, > i.e. trans_ADDI and trans_PADDI had the same signature and just forwarded their > arguments to a third method that does the real work. Is this kind of approach > desirable? We initially achieved this by using const_elt to set r=0 for addi, > which is not particularly nice, but we can look for other solutions. Yes, I could have tried harder to share the implementation here. And in retrospect, using a &PLS_D argument set for the non-prefixed integer load/store insns would have been fairly easy, and reduce 30 lines of unnecessary duplication. For the MMIRR prefixed instructions, that pain of duplication would be a lot higher. r~
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index b175441209..878d2f2f66 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -16,3 +16,11 @@ # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, see <http://www.gnu.org/licenses/>. # + +&D rt ra si +@D ...... rt:5 ra:5 si:s16 &D + +### Fixed-Point Arithmetic Instructions + +ADDI 001110 ..... ..... ................ @D +ADDIS 001111 ..... ..... ................ @D diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 9fc45d0614..68ed2cbff8 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -16,3 +16,17 @@ # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, see <http://www.gnu.org/licenses/>. # + +# Format MLS:D and 8LS:D +&PLS_D rt ra si r + +%pls_si 32:s18 0:16 + +@PLS_D ...... .. ... r:1 .. .................. \ + ...... rt:5 ra:5 ................ \ + &PLS_D si=%pls_si + +### Fixed-Point Arithmetic Instructions + +PADDI 000001 10 0--.-- .................. \ + 001110 ..... ..... ................ @PLS_D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 83f08950b4..6edde6a53d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -937,19 +937,6 @@ GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); /* addze addze. addzeo addzeo.*/ GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) -/* addi */ -static void gen_addi(DisasContext *ctx) -{ - target_long simm = SIMM(ctx->opcode); - - if (rA(ctx->opcode) == 0) { - /* li case */ - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); - } else { - tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rA(ctx->opcode)], simm); - } -} /* addic addic.*/ static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) { @@ -969,20 +956,6 @@ static void gen_addic_(DisasContext *ctx) gen_op_addic(ctx, 1); } -/* addis */ -static void gen_addis(DisasContext *ctx) -{ - target_long simm = SIMM(ctx->opcode); - - if (rA(ctx->opcode) == 0) { - /* lis case */ - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); - } else { - tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rA(ctx->opcode)], simm << 16); - } -} - /* addpcis */ static void gen_addpcis(DisasContext *ctx) { @@ -7034,10 +7007,8 @@ GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), -GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index b740083605..76e1832297 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -16,3 +16,45 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see <http://www.gnu.org/licenses/>. */ + +/* + * Incorporate CIA into the constant when R=1. + * Validate that when R=1, RA=0. + */ +static bool resolve_PLS_D(DisasContext *ctx, arg_PLS_D *a) +{ + if (a->r) { + a->si += ctx->cia; + return a->ra == 0; + } + return true; +} + +static bool trans_ADDI(DisasContext *ctx, arg_D *a) +{ + if (a->ra) { + tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si); + } else { + tcg_gen_movi_tl(cpu_gpr[a->rt], a->si); + } + return true; +} + +static bool trans_ADDIS(DisasContext *ctx, arg_D *a) +{ + a->si <<= 16; + return trans_ADDI(ctx, a); +} + +static bool trans_PADDI(DisasContext *ctx, arg_PLS_D *a) +{ + if (!resolve_PLS_D(ctx, a)) { + return false; + } + if (a->ra) { + tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si); + } else { + tcg_gen_movi_tl(cpu_gpr[a->rt], a->si); + } + return true; +}