From patchwork Fri Apr 16 18:59:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422570 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp653508jaf; Fri, 16 Apr 2021 12:11:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz7SE+NIEOMUm7tq7hKvE4rgkPpTVmkpAfutmolTTB8pHtyQxcydchpb2lN9PlMjqnKq5bj X-Received: by 2002:a7b:c10e:: with SMTP id w14mr9482535wmi.8.1618600288278; Fri, 16 Apr 2021 12:11:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600288; cv=none; d=google.com; s=arc-20160816; b=hpyonpujZNHI2EtBsH33MrWjUIegmbEhSWS+2SRDNUQ/nVPOJZEiJ+FM5PLYRpvvwl Cyj1U8AAhG3FEk5AgoC8Qh5UjolgeM5opN64Yls/75pe8qpq3y4GCNjpHHUFHrHIwTAf 3Z5pKlHMeLWgM1VSQLTt+Z2U86ZNGlP4dLn3C0CbLjzhybP9/CZU4fOLQyjgZ5VfpCt9 0qnm9y1bJSKP87QYvA1/UZXvzzm3JpdsstAywetyGXqAUSq1P+JBu/3ZYuIslmFkxoWI fXBGgV28bPMs+Y6FBJ97D3tGobZ2K+79seZwtA+3uc5DhlJYRFirFtS8IgYCckT5596c VmiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cT3QO7VItfU2VrQhqJUimeA2gkAab7Ike6sYupHt1Ns=; b=vTBpwbDU2FICNC/rgCRSOvM3cQ7xx1atFfEhRuOpqh+xCbmv3aWP9ivsI8e4yrqGlr jPNlOCdxdJRAip2o9KFVFa180cxL4p2tixa6mZQyHDuBgfH2BGIB2a74W4EKqFdi22Av kx0s6l9a7ntzR3kOcKq6+3n3wpyEjsJBu4DkRs6M3BTea0yq/uR3kaAVJvdJJdh5TY8C k+d3xAn8rCHmjRLChXl49cIm4t1wDlb6Q6LzNJMMB/gl0jOkSUCcRdJMTrHShMuI1fme stESqtzOZ7OlCKNHEM3uINGsQNFD6Mke3Egp4Bb0j8vuTnPTxLdHZwnETW8TN/uhjmtN SB/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OfrSZ+OM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c10si1163858wrr.68.2021.04.16.12.11.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:11:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OfrSZ+OM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60172 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTsD-0006w4-67 for patch@linaro.org; Fri, 16 Apr 2021 15:11:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXTha-0003Tj-LX for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:28 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:36424) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThI-0004H8-HC for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:26 -0400 Received: by mail-pl1-x62f.google.com with SMTP id z22so9349577plo.3 for ; Fri, 16 Apr 2021 12:00:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cT3QO7VItfU2VrQhqJUimeA2gkAab7Ike6sYupHt1Ns=; b=OfrSZ+OMHSbYGaGqVds/CA0XLpHG8fQUkcOxqjtCIRNJvla5b0ZpPGx698A9KZv1RX 9Lko5708APj3y2qm6pVVPSpJ2R2oqPApUidWVyeQcma9ZOrPreUoMXfmdsx4y5kRVofy 1LhY1AHZHMY/vQwsFJdjaYwrn6akSs5DgehiaCX9Vdzpu8McgoLyWZtuT7N+u3UjE720 K0jE4Pi6M8QMcgKYe8YE1aM8TN3Zszi40+D/DKI57nLhmUYxafJyUasLw4fGX/o/JDAc pVDU5DZQ0/6MwvVTVFnzSpmbQWmOpzu72LmX8ToH6/dzmZfFIGZ95/iFUrXe/BkFA50x jjQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cT3QO7VItfU2VrQhqJUimeA2gkAab7Ike6sYupHt1Ns=; b=izBddjLQiF7uSquc4eLQJDrLNqdHfNnBlzsnBraPzjaYpVQTupHnO9cYw/H5o431Zx aMAKUE1PZEoM/4LiVtG/msE/Yu+sKTCQ+J9w0yLYoudGyKZjn8543JRUfRbvrw9dELo7 i0N1ICTRQun+Ku7g4Y+opZwO0gO1+lfdT8hdm2Xsl7zh9W2keZ5HlwmO5kxZZMKluxgX tjChqMuEC1HQx/7zHnFJtIfzCPAuZyx4DaOyxJLHIwJQlyjXvsXmaL8xwkCay063OSj5 6vp2FUOcLB/I7qgLMuRFrYrFf8gZlggqaf0GLTR+RABB9GX02xz3IcS80shXo9hPbYrG nunw== X-Gm-Message-State: AOAM530cUQwR3/hTHHJwL2lIOV1Pj52tW8wvfaW9p17K5xGrP3b/pOjc L+LMSqXCvUru4ceLNmmOIkqYvci/8yu4BQ== X-Received: by 2002:a17:90a:a22:: with SMTP id o31mr11466660pjo.127.1618599607144; Fri, 16 Apr 2021 12:00:07 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/30] target/arm: Move TBFLAG_AM32 bits to the top Date: Fri, 16 Apr 2021 11:59:36 -0700 Message-Id: <20210416185959.1520974-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that these bits have been moved out of tb->flags, where TBFLAG_ANY was filling from the top, move AM32 to fill from the top, and A32 and M32 to fill from the bottom. This means fewer changes when adding new bits. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a8da7c55a6..15104e1440 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3395,13 +3395,13 @@ typedef ARMCPU ArchCPU; * * The bits for 32-bit A-profile and M-profile partially overlap: * - * 18 9 0 - * +----------------+--------------+ - * | TBFLAG_A32 | | - * +-----+----------+ TBFLAG_AM32 | - * | |TBFLAG_M32| | - * +-----+----------+--------------+ - * 14 9 0 + * 31 23 11 10 0 + * +-------------+----------+----------------+ + * | | | TBFLAG_A32 | + * | TBFLAG_AM32 | +-----+----------+ + * | | |TBFLAG_M32| + * +-------------+----------------+----------+ + * 31 23 5 4 0 * * Unless otherwise noted, these bits are cached in env->hflags. */ @@ -3418,44 +3418,44 @@ FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) /* * Bit usage when in AArch32 state, both A- and M-profile. */ -FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */ -FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */ +FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ +FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ /* * Bit usage when in AArch32 state, for A-profile only. */ -FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */ -FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ +FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ /* * We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime. This shares the same bits as * VECSTRIDE, which is OK as no XScale CPU has VFP. * Not cached, because VECLEN+VECSTRIDE are not cached. */ -FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) -FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */ -FIELD(TBFLAG_A32, SCTLR__B, 15, 1) /* Cannot overlap with SCTLR_B */ -FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) +FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ +FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ +FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) /* * Indicates whether cp register reads and writes by guest code should access * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! */ -FIELD(TBFLAG_A32, NS, 17, 1) +FIELD(TBFLAG_A32, NS, 10, 1) /* * Bit usage when in AArch32 state, for M-profile only. */ /* Handler (ie not Thread) mode */ -FIELD(TBFLAG_M32, HANDLER, 9, 1) +FIELD(TBFLAG_M32, HANDLER, 0, 1) /* Whether we should generate stack-limit checks */ -FIELD(TBFLAG_M32, STACKCHECK, 10, 1) +FIELD(TBFLAG_M32, STACKCHECK, 1, 1) /* Set if FPCCR.LSPACT is set */ -FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */ +FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ /* Set if we must create a new FP context */ -FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */ +FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ /* Set if FPCCR.S does not match current security state */ -FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */ +FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ /* * Bit usage when in AArch64 state