From patchwork Tue Apr 6 17:40:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 415934 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4785191jai; Tue, 6 Apr 2021 10:47:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw/85c6w2n1gwXz90LuCu3lyxKS/FvCOBVVSo9Y34VeUO2YpxJWCBfePQzK9stviC65F4tF X-Received: by 2002:a6b:650f:: with SMTP id z15mr24477166iob.128.1617731238920; Tue, 06 Apr 2021 10:47:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617731238; cv=none; d=google.com; s=arc-20160816; b=xS1EmBltLJR419dOFYT5Yw8TLmNHYjTvxb3f3GEdAyEkHdOSLYFLURv1RKz0lZbij1 xesDbI646q9tbP+6/Q9brgnaPXANL9y72HGMqJziODICOJj02oHgekcTav8Lt2UeOdLF 5TmFQv9HIGCC/mkkuSLsetZN5+Ycidzg3EIkGC+ddWcszdJ0nzhRQ1DgdkJRHYzEEZ38 eTpyHHbBe6vdNEwrLz7AfKp6VAnMh30efpK+DlkdrlS3IV86SoIenpFK68akd282ay7e Dcm7GkRsC+CE2xz0vHFu58jmQ4Ln0NjkNGDtfxruANapSgRmh5Hbewj3gDS6wXsjF1Vv Nw8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bmRgp+hz0GAy8sBEmRvnPYPMAtwbiJML48v1bJslbg4=; b=WUZ/00Dlz5pRBQgNSDHR0Prp9P8q0S9TbYYwjwgOqpFO7CUO7/HKus/2kkfTaNv9or ZKLq5UlUfkryXern84byEZzfmwaCof3IRmc77MLBWt1rzfMv4/M6Usa5xM06votIpztA rUhmqJg+wjH8Zlhq5p4MdAXmu5W2qj8Q6ik7FV3IvTddG+1+Y5e7M+tsC7YNB2KSirkp 2YH4Ori9NvbQ3LYDlcmakQjeSbAPhg8sZfFYCqw0fdgMepC3BG4k/IMy/ZAxmz9gpTI3 9f1PArq/FoVsAVVKlHSF/zHnmlPbDB6YSdazh17NyErfwrVYWqgKnApms46RfiF7GzmU Va5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O9BipY2W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v6si19603097jas.90.2021.04.06.10.47.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Apr 2021 10:47:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O9BipY2W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lTpnK-00007v-5R for patch@linaro.org; Tue, 06 Apr 2021 13:47:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45824) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lTpgw-0001iB-UJ for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:42 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:39518) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lTpgt-0006L4-W2 for qemu-devel@nongnu.org; Tue, 06 Apr 2021 13:40:42 -0400 Received: by mail-pj1-x102a.google.com with SMTP id ot17-20020a17090b3b51b0290109c9ac3c34so10054206pjb.4 for ; Tue, 06 Apr 2021 10:40:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bmRgp+hz0GAy8sBEmRvnPYPMAtwbiJML48v1bJslbg4=; b=O9BipY2WU4pSGlOlhX/14k5F3S8mHtQQ7IXOFREecGcmHEoViXZCQNOueXwQH9FGWs MQF4gBLIYXgoWsM+BKYf1KGcpmewgOIQB74fn9dwh5sEo9ipr+mejKzzNqE2W2KJ3Yze sOA9swCnbSZIX/sk1VgGIAeQkdFLtMXi9h+7Nwr7RJDMGUO8KsK3jrLmU/qV70qlk/Nj RZCqvg55wrbXAKT2+5WXEYMuIyY6diFG07jpTklBpT+P3/M3iYyQehoWHLWhxhm1kR/L kek7dVAnbuLjkzdRa2xaSMWcDv0HdQdbKPOTn64cEAViuu8gtS3MKcb06ZoLpZG1mUPy vp5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bmRgp+hz0GAy8sBEmRvnPYPMAtwbiJML48v1bJslbg4=; b=EsoWjqw4o8NOoIGLwAf8AgVbYB7YVnumf5Z5iI3LZ4WKeiohHtT2gYLruMweWZBk4m tpph76MSvnMOPvzX9rtfrimlRalKerXxd1A4qfALe0EDXrmKNa8K595Wd2+sjnAicX2W uKtcwsDCjyddxaITNVeTnUoiWUQACvUIPM6ffYz4RGwd3WXRhO5/fu+WWqn5k8zETkZX llgOtuxY9f5CRiQhsIpluy4bJSNHFzSy93D49yK7lz48sLLpcAXTW9sWgWJXSE01R2zn 8P88kE2Y1xbaUkSPqUtFctDYfGDcM3W/1FfyKZjZuvHRaIE8KfrSt1f0eX0WIylYRA+s su9Q== X-Gm-Message-State: AOAM531b1VYbxkV7fn4986+kmLbIUf7BrjopviPyzrLUhmeJ9o8F2Mqa Efk8y2eg+jk/Tm3ir5/CXwUiK9p6kfdU4Q== X-Received: by 2002:a17:90b:e18:: with SMTP id ge24mr5479320pjb.199.1617730838218; Tue, 06 Apr 2021 10:40:38 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id h15sm19148056pfo.20.2021.04.06.10.40.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 10:40:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/12] target/arm: Fix unaligned checks for mte_check1, mte_probe1 Date: Tue, 6 Apr 2021 10:40:24 -0700 Message-Id: <20210406174031.64299-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210406174031.64299-1-richard.henderson@linaro.org> References: <20210406174031.64299-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We were incorrectly assuming that only the first byte of an MTE access is checked against the tags. But per the ARM, unaligned accesses are pre-decomposed into single-byte accesses. So by the time we reach the actual MTE check in the ARM pseudocode, all accesses are aligned. We cannot tell a priori whether or not a given scalar access is aligned, therefore we must at least check. Use mte_probe_int, which is already set up for checking multiple granules. Buglink: https://bugs.launchpad.net/bugs/1921948 Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 109 +++++++++++++--------------------------- 1 file changed, 35 insertions(+), 74 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée Tested-by: Alex Bennée diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 144bfa4a51..619c4b9351 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -617,80 +617,6 @@ static void mte_check_fail(CPUARMState *env, uint32_t desc, } } -/* - * Perform an MTE checked access for a single logical or atomic access. - */ -static bool mte_probe1_int(CPUARMState *env, uint32_t desc, uint64_t ptr, - uintptr_t ra, int bit55) -{ - int mem_tag, mmu_idx, ptr_tag, size; - MMUAccessType type; - uint8_t *mem; - - ptr_tag = allocation_tag_from_addr(ptr); - - if (tcma_check(desc, bit55, ptr_tag)) { - return true; - } - - mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); - type = FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_LOAD; - size = FIELD_EX32(desc, MTEDESC, ESIZE); - - mem = allocation_tag_mem(env, mmu_idx, ptr, type, size, - MMU_DATA_LOAD, 1, ra); - if (!mem) { - return true; - } - - mem_tag = load_tag1(ptr, mem); - return ptr_tag == mem_tag; -} - -/* - * No-fault version of mte_check1, to be used by SVE for MemSingleNF. - * Returns false if the access is Checked and the check failed. This - * is only intended to probe the tag -- the validity of the page must - * be checked beforehand. - */ -bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr) -{ - int bit55 = extract64(ptr, 55, 1); - - /* If TBI is disabled, the access is unchecked. */ - if (unlikely(!tbi_check(desc, bit55))) { - return true; - } - - return mte_probe1_int(env, desc, ptr, 0, bit55); -} - -uint64_t mte_check1(CPUARMState *env, uint32_t desc, - uint64_t ptr, uintptr_t ra) -{ - int bit55 = extract64(ptr, 55, 1); - - /* If TBI is disabled, the access is unchecked, and ptr is not dirty. */ - if (unlikely(!tbi_check(desc, bit55))) { - return ptr; - } - - if (unlikely(!mte_probe1_int(env, desc, ptr, ra, bit55))) { - mte_check_fail(env, desc, ptr, ra); - } - - return useronly_clean_ptr(ptr); -} - -uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) -{ - return mte_check1(env, desc, ptr, GETPC()); -} - -/* - * Perform an MTE checked access for multiple logical accesses. - */ - /** * checkN: * @tag: tag memory to test @@ -882,6 +808,41 @@ uint64_t HELPER(mte_checkN)(CPUARMState *env, uint32_t desc, uint64_t ptr) return mte_checkN(env, desc, ptr, GETPC()); } +uint64_t mte_check1(CPUARMState *env, uint32_t desc, + uint64_t ptr, uintptr_t ra) +{ + uint64_t fault; + uint32_t total = FIELD_EX32(desc, MTEDESC, ESIZE); + int ret = mte_probe_int(env, desc, ptr, ra, total, &fault); + + if (unlikely(ret == 0)) { + mte_check_fail(env, desc, fault, ra); + } else if (ret < 0) { + return ptr; + } + return useronly_clean_ptr(ptr); +} + +uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) +{ + return mte_check1(env, desc, ptr, GETPC()); +} + +/* + * No-fault version of mte_check1, to be used by SVE for MemSingleNF. + * Returns false if the access is Checked and the check failed. This + * is only intended to probe the tag -- the validity of the page must + * be checked beforehand. + */ +bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr) +{ + uint64_t fault; + uint32_t total = FIELD_EX32(desc, MTEDESC, ESIZE); + int ret = mte_probe_int(env, desc, ptr, 0, total, &fault); + + return ret != 0; +} + /* * Perform an MTE checked access for DC_ZVA. */