Message ID | 20210317153444.310566-34-richard.henderson@linaro.org |
---|---|
State | Accepted |
Commit | db492ebb91059b818d5b5ea5975d227e5c3c9bcc |
Headers | show
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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id i11sm8271154otp.76.2021.03.17.08.35.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 08:35:19 -0700 (PDT) From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 33/38] tcg/tci: Split out tcg_out_op_rrrr Date: Wed, 17 Mar 2021 09:34:39 -0600 Message-Id: <20210317153444.310566-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org> References: <20210317153444.310566-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org> |
Series |
tcg patch queue for 6.0
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expand
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diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 20dd186b84..1e98c73417 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -399,6 +399,20 @@ static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, } #if TCG_TARGET_REG_BITS == 32 +static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, + TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) +{ + uint8_t *old_code_ptr = s->code_ptr; + + tcg_out_op_t(s, op); + tcg_out_r(s, r0); + tcg_out_r(s, r1); + tcg_out_r(s, r2); + tcg_out_r(s, r3); + + old_code_ptr[1] = s->code_ptr - old_code_ptr; +} + static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3, TCGReg r4, TCGCond c5) @@ -632,12 +646,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, old_code_ptr[1] = s->code_ptr - old_code_ptr; break; case INDEX_op_mulu2_i32: - tcg_out_op_t(s, opc); - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out_r(s, args[3]); - old_code_ptr[1] = s->code_ptr - old_code_ptr; + tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); break; #endif