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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 14/16] hw/ppc: Use hreg_store_msr for msr updates Date: Sun, 14 Mar 2021 11:59:04 -0600 Message-Id: <20210314175906.1733746-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f29; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, Greg Kurz , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Only one of the three places in hw/ppc that modify msr updated hflags. Even in that case, use the official interface instead of a direct call to hreg_compute_hflags. Signed-off-by: Richard Henderson --- Cc: Cédric Le Goater Cc: Greg Kurz --- hw/ppc/pnv_core.c | 3 ++- hw/ppc/spapr_hcall.c | 3 +-- hw/ppc/spapr_rtas.c | 3 ++- 3 files changed, 5 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index bd2bf2e044..31f041b9c7 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -29,6 +29,7 @@ #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/xics.h" #include "hw/qdev-properties.h" +#include "helper_regs.h" static const char *pnv_core_cpu_typename(PnvCore *pc) { @@ -54,7 +55,7 @@ static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) */ env->gpr[3] = PNV_FDT_ADDR; env->nip = 0x10; - env->msr |= MSR_HVB; /* Hypervisor mode */ + hreg_store_msr(env, env->msr | MSR_HVB, true); /* Hypervisor mode */ env->spr[SPR_HRMOR] = pc->hrmor; diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 7b5cd3553c..a4f7a09ba8 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1055,8 +1055,7 @@ static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr, CPUState *cs = CPU(cpu); SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); - env->msr |= (1ULL << MSR_EE); - hreg_compute_hflags(env); + hreg_store_msr(env, env->msr | (1ULL << MSR_EE), false); if (spapr_cpu->prod) { spapr_cpu->prod = false; diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 8a79f9c628..b9a6b7ef30 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -51,6 +51,7 @@ #include "target/ppc/mmu-hash64.h" #include "target/ppc/mmu-book3s-v3.h" #include "migration/blocker.h" +#include "helper_regs.h" static void rtas_display_character(PowerPCCPU *cpu, SpaprMachineState *spapr, uint32_t token, uint32_t nargs, @@ -162,7 +163,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr, cpu_synchronize_state(CPU(newcpu)); - env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME); + hreg_store_msr(env, (1ULL << MSR_SF) | (1ULL << MSR_ME), true); /* Enable Power-saving mode Exit Cause exceptions for the new CPU */ lpcr = env->spr[SPR_LPCR];