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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id c127sm10216240qkd.87.2021.03.14.10.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Mar 2021 10:59:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 09/16] target/ppc: Put dbcr0 single-step bits into hflags Date: Sun, 14 Mar 2021 11:58:59 -0600 Message-Id: <20210314175906.1733746-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210314175906.1733746-1-richard.henderson@linaro.org> References: <20210314175906.1733746-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72f; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ivan@vmfacility.fr, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because these bits were not in hflags, the code generated for single-stepping on BookE was essentially random. Recompute hflags when storing to dbcr0. Signed-off-by: Richard Henderson --- target/ppc/helper_regs.c | 20 +++++++++++++++----- target/ppc/misc_helper.c | 3 +++ target/ppc/translate.c | 11 ----------- 3 files changed, 18 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 0a746bffd7..c735540333 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -107,11 +107,21 @@ void hreg_compute_hflags(CPUPPCState *env) hflags |= le << MSR_LE; } - if (ppc_flags & POWERPC_FLAG_BE) { - msr_mask |= 1 << MSR_BE; - } - if (ppc_flags & POWERPC_FLAG_SE) { - msr_mask |= 1 << MSR_SE; + if (ppc_flags & POWERPC_FLAG_DE) { + target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; + if (dbcr0 & DBCR0_ICMP) { + hflags |= 1 << HFLAGS_SE; + } + if (dbcr0 & DBCR0_BRT) { + hflags |= 1 << HFLAGS_BE; + } + } else { + if (ppc_flags & POWERPC_FLAG_BE) { + msr_mask |= 1 << MSR_BE; + } + if (ppc_flags & POWERPC_FLAG_SE) { + msr_mask |= 1 << MSR_SE; + } } if (msr_is_64bit(env, msr)) { diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index b04b4d7c6e..a5ee1fd63c 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -215,6 +215,9 @@ void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val) { + /* Bits 26 & 27 affect single-stepping */ + hreg_compute_hflags(env); + /* Bits 28 & 29 affect reset or shutdown. */ store_40x_dbcr0(env, val); } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a85b890bb0..7912495f28 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7923,17 +7923,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) if ((hflags >> HFLAGS_BE) & 1) { ctx->singlestep_enabled |= CPU_BRANCH_STEP; } - if ((env->flags & POWERPC_FLAG_DE) && msr_de) { - ctx->singlestep_enabled = 0; - target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; - if (dbcr0 & DBCR0_ICMP) { - ctx->singlestep_enabled |= CPU_SINGLE_STEP; - } - if (dbcr0 & DBCR0_BRT) { - ctx->singlestep_enabled |= CPU_BRANCH_STEP; - } - - } if (unlikely(ctx->base.singlestep_enabled)) { ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; }