diff mbox series

[v4,78/78] target/arm: Enable SVE2 and some extensions

Message ID	20210309162041.23124-79-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH v4 78/78] target/arm: Enable SVE2 and some extensions Date: Tue, 9 Mar 2021 08:20:41 -0800 Message-Id: <20210309162041.23124-79-richard.henderson@linaro.org> In-Reply-To: <20210309162041.23124-1-richard.henderson@linaro.org> References: <20210309162041.23124-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Implement SVE2 \| expand [v4,00/78] target/arm: Implement SVE2 [v4,01/78] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 [v4,02/78] target/arm: Implement SVE2 Integer Multiply - Unpredicated [v4,03/78] target/arm: Implement SVE2 integer pairwise add and accumulate long [v4,04/78] target/arm: Implement SVE2 integer unary operations (predicated) [v4,05/78] target/arm: Split out saturating/rounding shifts from neon [v4,06/78] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated) [v4,07/78] target/arm: Implement SVE2 integer halving add/subtract (predicated) [v4,08/78] target/arm: Implement SVE2 integer pairwise arithmetic [v4,09/78] target/arm: Implement SVE2 saturating add/subtract (predicated) [v4,10/78] target/arm: Implement SVE2 integer add/subtract long [v4,11/78] target/arm: Implement SVE2 integer add/subtract interleaved long [v4,12/78] target/arm: Implement SVE2 integer add/subtract wide [v4,13/78] target/arm: Implement SVE2 integer multiply long [v4,14/78] target/arm: Implement PMULLB and PMULLT [v4,15/78] target/arm: Implement SVE2 bitwise shift left long [v4,16/78] target/arm: Implement SVE2 bitwise exclusive-or interleaved [v4,17/78] target/arm: Implement SVE2 bitwise permute [v4,18/78] target/arm: Implement SVE2 complex integer add [v4,19/78] target/arm: Implement SVE2 integer absolute difference and accumulate long [v4,20/78] target/arm: Implement SVE2 integer add/subtract long with carry [v4,21/78] target/arm: Implement SVE2 bitwise shift right and accumulate [v4,22/78] target/arm: Implement SVE2 bitwise shift and insert [v4,23/78] target/arm: Implement SVE2 integer absolute difference and accumulate [v4,24/78] target/arm: Implement SVE2 saturating extract narrow [v4,25/78] target/arm: Implement SVE2 floating-point pairwise [v4,26/78] target/arm: Implement SVE2 SHRN, RSHRN [v4,27/78] target/arm: Implement SVE2 SQSHRUN, SQRSHRUN [v4,28/78] target/arm: Implement SVE2 UQSHRN, UQRSHRN [v4,29/78] target/arm: Implement SVE2 SQSHRN, SQRSHRN [v4,30/78] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS [v4,31/78] target/arm: Implement SVE2 WHILERW, WHILEWR [v4,32/78] target/arm: Implement SVE2 bitwise ternary operations [v4,33/78] target/arm: Implement SVE2 MATCH, NMATCH [v4,34/78] target/arm: Implement SVE2 saturating multiply-add long [v4,35/78] target/arm: Implement SVE2 saturating multiply-add high [v4,36/78] target/arm: Implement SVE2 integer multiply-add long [v4,37/78] target/arm: Implement SVE2 complex integer multiply-add [v4,38/78] target/arm: Implement SVE2 ADDHNB, ADDHNT [v4,39/78] target/arm: Implement SVE2 RADDHNB, RADDHNT [v4,40/78] target/arm: Implement SVE2 SUBHNB, SUBHNT [v4,41/78] target/arm: Implement SVE2 RSUBHNB, RSUBHNT [v4,42/78] target/arm: Implement SVE2 HISTCNT, HISTSEG [v4,43/78] target/arm: Implement SVE2 XAR [v4,44/78] target/arm: Implement SVE2 scatter store insns [v4,45/78] target/arm: Implement SVE2 gather load insns [v4,46/78] target/arm: Implement SVE2 FMMLA [v4,47/78] target/arm: Implement SVE2 SPLICE, EXT [v4,48/78] target/arm: Pass separate addend to {U, S}DOT helpers [v4,49/78] target/arm: Pass separate addend to FCMLA helpers [v4,50/78] target/arm: Split out formats for 2 vectors + 1 index [v4,51/78] target/arm: Split out formats for 3 vectors + 1 index [v4,52/78] target/arm: Implement SVE2 integer multiply (indexed) [v4,53/78] target/arm: Implement SVE2 integer multiply-add (indexed) [v4,54/78] target/arm: Implement SVE2 saturating multiply-add high (indexed) [v4,55/78] target/arm: Implement SVE2 saturating multiply-add (indexed) [v4,56/78] target/arm: Implement SVE2 integer multiply long (indexed) [v4,57/78] target/arm: Implement SVE2 saturating multiply (indexed) [v4,58/78] target/arm: Implement SVE2 signed saturating doubling multiply high [v4,59/78] target/arm: Implement SVE2 saturating multiply high (indexed) [v4,60/78] target/arm: Implement SVE2 multiply-add long (indexed) [v4,61/78] target/arm: Implement SVE2 complex integer multiply-add (indexed) [v4,62/78] target/arm: Implement SVE mixed sign dot product (indexed) [v4,63/78] target/arm: Implement SVE mixed sign dot product [v4,64/78] target/arm: Implement SVE2 crypto unary operations [v4,65/78] target/arm: Implement SVE2 crypto destructive binary operations [v4,66/78] target/arm: Implement SVE2 crypto constructive binary operations [v4,67/78] target/arm: Implement SVE2 TBL, TBX [v4,68/78] target/arm: Implement SVE2 FCVTNT [v4,69/78] target/arm: Implement SVE2 FCVTLT [v4,70/78] target/arm: Implement SVE2 FCVTXNT, FCVTX [v4,71/78] target/arm: Implement SVE2 FLOGB [v4,72/78] target/arm: Share table of sve load functions [v4,73/78] target/arm: Implement SVE2 LD1RO [v4,74/78] target/arm: Implement 128-bit ZIP, UZP, TRN [v4,75/78] target/arm: Implement SVE2 bitwise shift immediate [v4,76/78] target/arm: Implement SVE2 fp multiply-add long [v4,77/78] target/arm: Implement SVE2 complex integer dot product [v4,78/78] target/arm: Enable SVE2 and some extensions

Commit Message

Richard Henderson March 9, 2021, 4:20 p.m. UTC

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/cpu64.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

-- 
2.25.1

diff mbox series

Patch

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f0a9e968c9..b717b096c3 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -702,6 +702,17 @@  static void aarch64_max_initfn(Object *obj)
         t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
         cpu->isar.id_aa64mmfr2 = t;
 
+        t = cpu->isar.id_aa64zfr0;
+        t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
+        t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);  /* PMULL */
+        t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
+        t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
+        t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
+        t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
+        t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
+        t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
+        cpu->isar.id_aa64zfr0 = t;
+
         /* Replicate the same data to the 32-bit id registers.  */
         u = cpu->isar.id_isar5;
         u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */