From patchwork Tue Mar 9 16:20:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 396039 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2791289jai; Tue, 9 Mar 2021 09:51:21 -0800 (PST) X-Google-Smtp-Source: ABdhPJxx11oHYvA4UqgvAQVSiAhIxC0q7KUQdwPUZUs4whppdv4nZrC1heUUTzuFJBevLOFkpRD8 X-Received: by 2002:a05:620a:12da:: with SMTP id e26mr7955702qkl.92.1615312281267; Tue, 09 Mar 2021 09:51:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615312281; cv=none; d=google.com; s=arc-20160816; b=d2okSNXXwl45y9HrHT0GLMnKkU2Agqb1VpHnCAXjPYMnyOVOwoLK1/u7O9uE1rBp6X lSXBIjCKv4PIaMRfRHumomuQaUq0AlcQRNYVCb1GepUcCKEAl7l02BIttUqiKhff5pJT ileDJW1mkwGcFeMb7yrSH6xE6Fzcg9rAZZPrz7+9AD9a9YsC/6LTKwoAp8SD9MlogSbY rFHPPFhB6PEzsA3uzGyDdjtSf2qEfS/v8Pib8uP/juralrS04Ki1jxfIwf7b9Lv7J6K3 HaowMINnC717Ic2p1HObJTIUXc1HOwlkNsICK5M9vmrNF7GXzXm4Fh5Oa2UJY6EIvh0g dQQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=r8qWPPJzVA86rxlts7U6E1EFTR6n39CVbZo89lBzbCI=; b=i2zWjVh/243q+0KTOVcn71yjyWuj+Er/gEeiTRt/egLD0838HAiisdN2rmjI91rkjH tsNHjPMkW00WcV1qciflm2XzcGpIoHZlaL3vX7lR4OIraYaFpPwj1hSXCCJrRx4tKfut AAwsxLoUWuazYi+HaRKF8+xlydT0Akra4rMPr5/wfOlUq1LhIjpmeMj3PwSaNBucB40g pFOE48kH/azXR1LBm6URM1RODnpA+7Ycyyfncbdxsi7C1o2AKbb1nKIbdo+iitYunGdZ SD6f3f4OppPDN536XfZueqSaZcCMeWNtGmoVSelEMUPakZnjBAnq/uB0jBHTfKfCDQXC g4fQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YczDUld1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h5si8120344qvm.59.2021.03.09.09.51.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 09 Mar 2021 09:51:21 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YczDUld1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJgVs-0004np-Jb for patch@linaro.org; Tue, 09 Mar 2021 12:51:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46684) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJf7Z-0000GJ-TW for qemu-devel@nongnu.org; Tue, 09 Mar 2021 11:22:09 -0500 Received: from mail-oo1-xc31.google.com ([2607:f8b0:4864:20::c31]:33228) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lJf7X-0002l6-Qo for qemu-devel@nongnu.org; Tue, 09 Mar 2021 11:22:09 -0500 Received: by mail-oo1-xc31.google.com with SMTP id z22so3178561oop.0 for ; Tue, 09 Mar 2021 08:22:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r8qWPPJzVA86rxlts7U6E1EFTR6n39CVbZo89lBzbCI=; b=YczDUld1qtyPKcICrQV1pUYue/CPwvzw0XK91yJMR1F1MltJMHLoY4eekTASUymXne 77XzisG7vPMk0kB3nkackK91l1jldzZuW8tJBd5eGo21L05ROt4cOwPlFGF36AaeuaCB Eyq82kEz2saWhlIXdw7frQoxM3DuGm1WiBCGLxn29IJ63P0Z6M43YRWR1n1aMq1LGbuu 2wIN499cDVKBkhfvPiWKMVcDwkpRhmnOIapTFijF2I/57Nx9+6tGn/8cbl7Kwlx7/+Wz 9LpI54H5WD1cpWJDtRGgfcQ5GUbFJBv8bGrCwOX7ZVP6AsVaG8FTdYade6lF3PFfDlt7 tx4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r8qWPPJzVA86rxlts7U6E1EFTR6n39CVbZo89lBzbCI=; b=ikxUijiDmAzZIsEsS/UrhgeFOTDyz3N8tUSgf2gsEuiioh/VLCK7WAs3cpG+vQtlwB yr8esKggxwFNPTgasykrdcHLT6B/4+JfOhAhBKplG7Oo/fMjDJDQ0IS44T96rpsxYrkL GLxxtt62jWgB7vhFv8I8tQ1OP9v07xksB0nkcwY6uqSXDohxuNuoQnTEma1Qnmg6ZNGf uhnh624yZZeXQBP6oA+hLSNxxyxLSjjBFzTcr8yKlpJEbYhQBibGtNK/4juX7miS1jlB K8pFSEL085Ju0l0rSYtbEOmCFMnp10Cp4w/+VEU6+UAneGqyhk6CgzgkslYgCogrfYQv FJxw== X-Gm-Message-State: AOAM530iS0rLuHnj1Wg5KOB3AUpiP1k7zmAw0RvfAZ114CN2f4cCJbbw OLGXWybaza2O48+QsJ37t4JvORmy2uSyUJdS X-Received: by 2002:a4a:9101:: with SMTP id k1mr8329364oog.7.1615306926693; Tue, 09 Mar 2021 08:22:06 -0800 (PST) Received: from localhost.localdomain (fixed-187-189-51-144.totalplay.net. [187.189.51.144]) by smtp.gmail.com with ESMTPSA id u19sm3470898ote.15.2021.03.09.08.22.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Mar 2021 08:22:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 46/78] target/arm: Implement SVE2 FMMLA Date: Tue, 9 Mar 2021 08:20:09 -0800 Message-Id: <20210309162041.23124-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210309162041.23124-1-richard.henderson@linaro.org> References: <20210309162041.23124-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c31; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org, Stephen Long Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200422165503.13511-1-steplong@quicinc.com> [rth: Fix indexing in helpers, expand macro to straight functions.] Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++++++ target/arm/helper-sve.h | 3 ++ target/arm/sve.decode | 4 +++ target/arm/sve_helper.c | 74 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 34 ++++++++++++++++++ 5 files changed, 125 insertions(+) -- 2.25.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 57d03addb4..3f19c4cbed 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4213,6 +4213,16 @@ static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; } +static inline bool isar_feature_aa64_sve2_f32mm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; +} + +static inline bool isar_feature_aa64_sve2_f64mm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 28b8f00201..7e99dcd119 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -2662,3 +2662,6 @@ DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index c3958bed6a..cb2ee86228 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1389,6 +1389,10 @@ UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx +### SVE2 floating point matrix multiply accumulate + +FMMLA 01100100 .. 1 ..... 111001 ..... ..... @rda_rn_rm + ### SVE2 Memory Gather Load Group # SVE2 64-bit gather non-temporal load diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 0a02deef70..fcfb7d1f41 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -7264,3 +7264,77 @@ void HELPER(sve2_xar_s)(void *vd, void *vn, void *vm, uint32_t desc) d[i] = ror32(n[i] ^ m[i], shr); } } + +void HELPER(fmmla_s)(void *vd, void *vn, void *vm, void *va, + void *status, uint32_t desc) +{ + intptr_t s, opr_sz = simd_oprsz(desc) / (sizeof(float32) * 4); + + for (s = 0; s < opr_sz; ++s) { + float32 *n = vn + s * sizeof(float32) * 4; + float32 *m = vm + s * sizeof(float32) * 4; + float32 *a = va + s * sizeof(float32) * 4; + float32 *d = vd + s * sizeof(float32) * 4; + float32 n00 = n[H4(0)], n01 = n[H4(1)]; + float32 n10 = n[H4(2)], n11 = n[H4(3)]; + float32 m00 = m[H4(0)], m01 = m[H4(1)]; + float32 m10 = m[H4(2)], m11 = m[H4(3)]; + float32 p0, p1; + + /* i = 0, j = 0 */ + p0 = float32_mul(n00, m00, status); + p1 = float32_mul(n01, m01, status); + d[H4(0)] = float32_add(a[H4(0)], float32_add(p0, p1, status), status); + + /* i = 0, j = 1 */ + p0 = float32_mul(n00, m10, status); + p1 = float32_mul(n01, m11, status); + d[H4(1)] = float32_add(a[H4(1)], float32_add(p0, p1, status), status); + + /* i = 1, j = 0 */ + p0 = float32_mul(n10, m00, status); + p1 = float32_mul(n11, m01, status); + d[H4(2)] = float32_add(a[H4(2)], float32_add(p0, p1, status), status); + + /* i = 1, j = 1 */ + p0 = float32_mul(n10, m10, status); + p1 = float32_mul(n11, m11, status); + d[H4(3)] = float32_add(a[H4(3)], float32_add(p0, p1, status), status); + } +} + +void HELPER(fmmla_d)(void *vd, void *vn, void *vm, void *va, + void *status, uint32_t desc) +{ + intptr_t s, opr_sz = simd_oprsz(desc) / (sizeof(float64) * 4); + + for (s = 0; s < opr_sz; ++s) { + float64 *n = vn + s * sizeof(float64) * 4; + float64 *m = vm + s * sizeof(float64) * 4; + float64 *a = va + s * sizeof(float64) * 4; + float64 *d = vd + s * sizeof(float64) * 4; + float64 n00 = n[0], n01 = n[1], n10 = n[2], n11 = n[3]; + float64 m00 = m[0], m01 = m[1], m10 = m[2], m11 = m[3]; + float64 p0, p1; + + /* i = 0, j = 0 */ + p0 = float64_mul(n00, m00, status); + p1 = float64_mul(n01, m01, status); + d[0] = float64_add(a[0], float64_add(p0, p1, status), status); + + /* i = 0, j = 1 */ + p0 = float64_mul(n00, m10, status); + p1 = float64_mul(n01, m11, status); + d[1] = float64_add(a[1], float64_add(p0, p1, status), status); + + /* i = 1, j = 0 */ + p0 = float64_mul(n10, m00, status); + p1 = float64_mul(n11, m01, status); + d[2] = float64_add(a[2], float64_add(p0, p1, status), status); + + /* i = 1, j = 1 */ + p0 = float64_mul(n10, m10, status); + p1 = float64_mul(n11, m11, status); + d[3] = float64_add(a[3], float64_add(p0, p1, status), status); + } +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 21ecb535ca..8c93d87897 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7673,6 +7673,40 @@ DO_SVE2_ZPZZ_FP(FMINP, fminp) * SVE Integer Multiply-Add (unpredicated) */ +static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a) +{ + gen_helper_gvec_4_ptr *fn; + + switch (a->esz) { + case MO_32: + if (!dc_isar_feature(aa64_sve2_f32mm, s)) { + return false; + } + fn = gen_helper_fmmla_s; + break; + case MO_64: + if (!dc_isar_feature(aa64_sve2_f64mm, s)) { + return false; + } + fn = gen_helper_fmmla_d; + break; + default: + return false; + } + + if (sve_access_check(s)) { + unsigned vsz = vec_full_reg_size(s); + TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); + tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + vec_full_reg_offset(s, a->ra), + status, vsz, vsz, 0, fn); + tcg_temp_free_ptr(status); + } + return true; +} + static bool do_sqdmlal_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel1, bool sel2) {