From patchwork Tue Mar 9 16:19:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 396024 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp2779153jai; Tue, 9 Mar 2021 09:34:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJzzHuB5q7h0yQLVbGu2I184GoXAoUX0dp9lxAhxFaOg0Hp/Ib42w9e6iNqhuTFml9wdJeIc X-Received: by 2002:a02:77d0:: with SMTP id g199mr28973858jac.118.1615311295278; Tue, 09 Mar 2021 09:34:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615311295; cv=none; d=google.com; s=arc-20160816; b=Bi01xUDT3lBhW86+dZv9en9vTJ1SsdgLjxpP3ddxme2XWWshcYeNIa5EjpOpWJDFA3 27a1Ryq/8BKm7g9feKRnLFqHIlPRJiedFvUSs3B62LUg/aHsghro212AjoFNCHs1n/e+ wyNY1gtFr+o0BWp50SkbzsoUZ2wWF5x9DeJaKcDr9quccMbX1gq6vAcYFSJGj7bMbv4o 3qmYPS+QPL9I6ILP7txRukuXdbgj9+Q7NzEUWfV6NIaPm1rx7hlcjLWjTRekli97co23 ezImiF6aHAQF10bVbbjNmE/pWZmHq6L8T2oVE1M9olhN/Yazx7RgAPJsvub+RCbweXvJ XRPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/w1/PeuZSTxpxUDHY11OvShK/rLcq0Hrz8JHi0g1Cbs=; b=zC+GQuG3Fhi4gptOOaJlytTOVTEbl1CQ5h5t4xgTpcljuTm2Tl5QwVOGHmNYQ6TCy9 Y2y4VCPiYvgedM4Cu/gCuni/6eCR5JNz8ge4k6FK3O8TRo6UzJFkjKUKB2klMS/gW6j+ bVqjlv4g+GkvpF7g72tAIGGUJOEFk5j42qpCXRl+PDiUWOoDs2kPlVE92ISV9f0kkHl5 7uOmMQeX21qOvvUpyXplweU9bmNPrISMfjHZiNYJ5GJP/aPA2zb3qxzGZOvFMUjd+Qn2 QI9kOdohUnNVyJQI39L65aY8RnMohrRxy1q48JZdh9HfuplW3kzBMUQCcdhOlilrnvJO 33WQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m4j39iVo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l9si13002781ilv.110.2021.03.09.09.34.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 09 Mar 2021 09:34:55 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m4j39iVo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57650 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJgFy-0005f3-Hl for patch@linaro.org; Tue, 09 Mar 2021 12:34:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45530) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJf6e-0007BB-Iu for qemu-devel@nongnu.org; Tue, 09 Mar 2021 11:21:12 -0500 Received: from mail-oi1-x229.google.com ([2607:f8b0:4864:20::229]:47063) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lJf6Q-0002Rm-V1 for qemu-devel@nongnu.org; Tue, 09 Mar 2021 11:21:12 -0500 Received: by mail-oi1-x229.google.com with SMTP id f3so15492345oiw.13 for ; Tue, 09 Mar 2021 08:20:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/w1/PeuZSTxpxUDHY11OvShK/rLcq0Hrz8JHi0g1Cbs=; b=m4j39iVowofGQn4C6GTtRO3E174pNhL4/3av0Ogvp29dTweGdQ2k/7KFd044+bFKal /SUda8AhNT3cFVqmsdXi/6E6d/4kH4CZvLuvto/N4ZFiLi7tDcpp8BXRKk5YHbEA6Xw0 7viJFsNwuQFmWboFm2y4ijiTsi5EadvWs7yjjLRQkSXOQnJDDdWDl7kPeBF/eiPUD+mX 9gQ5a5YGn6EbrNP/wxZjNRnXIbwQ+kMPoYKoN2vhOht7zWLhmsOEJkwsaLFcYbxlztHb D+Lv5Uy6sSFeXWb9sXimCuLxldx5dyZ7vQeHyoabC4JC6En1R45FSsVV86/7BCL+1ZzU LPrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/w1/PeuZSTxpxUDHY11OvShK/rLcq0Hrz8JHi0g1Cbs=; b=bWZhSeJ8uFfiqsLa1E4oxvZAsfFcisUOVms6stNe4qiPI/3upjXwjni/Z6r31ZM7UK BbBhkjoQ60i+ah1m3Zsby7BsYIwmqhwyvFZG2DWRVep57HLLpsa6BfUaRndV71ojoWtP TgGgddYj8ewpN93CgNbf7+bUOrKEqU1F7HjIpIvP8HDGSObrVuSBdFjtEghaeO/sA66z SlqH4rx5HM1TNkRThQPTorDKE4CWnW3vH0qX0I9BEnLYS1+rV4esq5hRvOeYO7C/lC5U Ds9HAU0KQIxPlxWpodEARI270AWS7RNzh7Zcs3N6I7htYHajN94yGESzed1yJD/MV2sV 2sUA== X-Gm-Message-State: AOAM530KaZRyW1MaGDqmLLujXPFSTP3cotgVpoFX181DEaBROHG8Rbdl +z87rloNajecqJSGhJZITPiUSD2wHaO9Us8A X-Received: by 2002:aca:b108:: with SMTP id a8mr3496355oif.49.1615306857898; Tue, 09 Mar 2021 08:20:57 -0800 (PST) Received: from localhost.localdomain (fixed-187-189-51-144.totalplay.net. [187.189.51.144]) by smtp.gmail.com with ESMTPSA id v23sm2516474ots.63.2021.03.09.08.20.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Mar 2021 08:20:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 13/78] target/arm: Implement SVE2 integer multiply long Date: Tue, 9 Mar 2021 08:19:36 -0800 Message-Id: <20210309162041.23124-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210309162041.23124-1-richard.henderson@linaro.org> References: <20210309162041.23124-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Exclude PMULL from this category for the moment. Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 15 +++++++++++++++ target/arm/sve.decode | 9 +++++++++ target/arm/sve_helper.c | 31 +++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 9 +++++++++ 4 files changed, 64 insertions(+) -- 2.25.1 diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 3286a9c205..ad8121eec6 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -2347,4 +2347,19 @@ DEF_HELPER_FLAGS_6(sve_stdd_le_zd_mte, TCG_CALL_NO_WG, DEF_HELPER_FLAGS_6(sve_stdd_be_zd_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmull_zzz_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmull_zzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmull_zzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_smull_zzz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_smull_zzz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_smull_zzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_umull_zzz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_umull_zzz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_umull_zzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(sve2_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index f6f21426ef..d9a72b7661 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1196,3 +1196,12 @@ SSUBWB 01000101 .. 0 ..... 010 100 ..... ..... @rd_rn_rm SSUBWT 01000101 .. 0 ..... 010 101 ..... ..... @rd_rn_rm USUBWB 01000101 .. 0 ..... 010 110 ..... ..... @rd_rn_rm USUBWT 01000101 .. 0 ..... 010 111 ..... ..... @rd_rn_rm + +## SVE2 integer multiply long + +SQDMULLB_zzz 01000101 .. 0 ..... 011 000 ..... ..... @rd_rn_rm +SQDMULLT_zzz 01000101 .. 0 ..... 011 001 ..... ..... @rd_rn_rm +SMULLB_zzz 01000101 .. 0 ..... 011 100 ..... ..... @rd_rn_rm +SMULLT_zzz 01000101 .. 0 ..... 011 101 ..... ..... @rd_rn_rm +UMULLB_zzz 01000101 .. 0 ..... 011 110 ..... ..... @rd_rn_rm +UMULLT_zzz 01000101 .. 0 ..... 011 111 ..... ..... @rd_rn_rm diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 5b7b8d27b8..7877a5bdf5 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -1154,6 +1154,37 @@ DO_ZZZ_TB(sve2_uabdl_h, uint16_t, uint8_t, H1_2, H1, DO_ABD) DO_ZZZ_TB(sve2_uabdl_s, uint32_t, uint16_t, H1_4, H1_2, DO_ABD) DO_ZZZ_TB(sve2_uabdl_d, uint64_t, uint32_t, , H1_4, DO_ABD) +DO_ZZZ_TB(sve2_smull_zzz_h, int16_t, int8_t, H1_2, H1, DO_MUL) +DO_ZZZ_TB(sve2_smull_zzz_s, int32_t, int16_t, H1_4, H1_2, DO_MUL) +DO_ZZZ_TB(sve2_smull_zzz_d, int64_t, int32_t, , H1_4, DO_MUL) + +DO_ZZZ_TB(sve2_umull_zzz_h, uint16_t, uint8_t, H1_2, H1, DO_MUL) +DO_ZZZ_TB(sve2_umull_zzz_s, uint32_t, uint16_t, H1_4, H1_2, DO_MUL) +DO_ZZZ_TB(sve2_umull_zzz_d, uint64_t, uint32_t, , H1_4, DO_MUL) + +/* Note that the multiply cannot overflow, but the doubling can. */ +static inline int16_t do_sqdmull_h(int16_t n, int16_t m) +{ + int16_t val = n * m; + return DO_SQADD_H(val, val); +} + +static inline int32_t do_sqdmull_s(int32_t n, int32_t m) +{ + int32_t val = n * m; + return DO_SQADD_S(val, val); +} + +static inline int64_t do_sqdmull_d(int64_t n, int64_t m) +{ + int64_t val = n * m; + return do_sqadd_d(val, val); +} + +DO_ZZZ_TB(sve2_sqdmull_zzz_h, int16_t, int8_t, H1_2, H1, do_sqdmull_h) +DO_ZZZ_TB(sve2_sqdmull_zzz_s, int32_t, int16_t, H1_4, H1_2, do_sqdmull_s) +DO_ZZZ_TB(sve2_sqdmull_zzz_d, int64_t, int32_t, , H1_4, do_sqdmull_d) + #undef DO_ZZZ_TB #define DO_ZZZ_WTB(NAME, TYPEW, TYPEN, HW, HN, OP) \ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index e88787318c..8da87a6ce0 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -6022,6 +6022,15 @@ DO_SVE2_ZZZ_TB(SADDLBT, saddl, false, true) DO_SVE2_ZZZ_TB(SSUBLBT, ssubl, false, true) DO_SVE2_ZZZ_TB(SSUBLTB, ssubl, true, false) +DO_SVE2_ZZZ_TB(SQDMULLB_zzz, sqdmull_zzz, false, false) +DO_SVE2_ZZZ_TB(SQDMULLT_zzz, sqdmull_zzz, true, true) + +DO_SVE2_ZZZ_TB(SMULLB_zzz, smull_zzz, false, false) +DO_SVE2_ZZZ_TB(SMULLT_zzz, smull_zzz, true, true) + +DO_SVE2_ZZZ_TB(UMULLB_zzz, umull_zzz, false, false) +DO_SVE2_ZZZ_TB(UMULLT_zzz, umull_zzz, true, true) + #define DO_SVE2_ZZZ_WTB(NAME, name, SEL2) \ static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \ { \