[PULL,22/27] tcg/tci: Merge mov, not and neg operations

Message ID	20210306213613.85168-23-richard.henderson@linaro.org
State	Accepted
Commit	9e9acb7b348570f8a9ed62fcbad299424fe61501
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 22/27] tcg/tci: Merge mov, not and neg operations Date: Sat, 6 Mar 2021 13:36:08 -0800 Message-Id: <20210306213613.85168-23-richard.henderson@linaro.org> In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg patch queue \| expand [PULL,00/27] tcg patch queue [PULL,01/27] tcg/aarch64: Fix constant subtraction in tcg_out_addsub2 [PULL,02/27] tcg/aarch64: Fix I3617_CMLE0 [PULL,03/27] tcg/aarch64: Fix generation of "scalar" vector operations [PULL,04/27] tcg/tci: Use exec/cpu_ldst.h interfaces [PULL,05/27] tcg: Split out tcg_raise_tb_overflow [PULL,06/27] tcg: Manage splitwx in tc_ptr_to_region_tree by hand [PULL,07/27] tcg/tci: Merge identical cases in generation (arithmetic opcodes) [PULL,08/27] tcg/tci: Merge identical cases in generation (exchange opcodes) [PULL,09/27] tcg/tci: Merge identical cases in generation (deposit opcode) [PULL,10/27] tcg/tci: Merge identical cases in generation (conditional opcodes) [PULL,11/27] tcg/tci: Merge identical cases in generation (load/store opcodes) [PULL,12/27] tcg/tci: Remove tci_read_r8 [PULL,13/27] tcg/tci: Remove tci_read_r8s [PULL,14/27] tcg/tci: Remove tci_read_r16 [PULL,15/27] tcg/tci: Remove tci_read_r16s [PULL,16/27] tcg/tci: Remove tci_read_r32 [PULL,17/27] tcg/tci: Remove tci_read_r32s [PULL,18/27] tcg/tci: Reduce use of tci_read_r64 [PULL,19/27] tcg/tci: Merge basic arithmetic operations [PULL,20/27] tcg/tci: Merge extension operations [PULL,21/27] tcg/tci: Merge bswap operations [PULL,22/27] tcg/tci: Merge mov, not and neg operations [PULL,23/27] accel/tcg: rename tb_lookup__cpu_state and hoist state extraction [PULL,24/27] accel/tcg: move CF_CLUSTER calculation to curr_cflags [PULL,25/27] accel/tcg: drop the use of CF_HASH_MASK and rename params [PULL,26/27] include/exec: lightly re-arrange TranslationBlock [PULL,27/27] accel/tcg: Precompute curr_cflags into cpu->tcg_cflags

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20210306213613.85168-23-richard.henderson@linaro.org

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9e9acb7b348570f8a9ed62fcbad299424fe61501

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 22/27] tcg/tci: Merge mov, not and neg operations
Date: Sat,  6 Mar 2021 13:36:08 -0800
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Series

tcg patch queue | expand

Commit Message

Richard Henderson March 6, 2021, 9:36 p.m. UTC

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 tcg/tci.c | 29 +++++------------------------
 1 file changed, 5 insertions(+), 24 deletions(-)

-- 
2.25.1

diff --git a/tcg/tci.c b/tcg/tci.c
index 66f2962d6e..3ccd30c39c 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -387,7 +387,7 @@  uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
             tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
             break;
 #endif
-        case INDEX_op_mov_i32:
+        CASE_32_64(mov)
             t0 = *tb_ptr++;
             t1 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, t1);
@@ -649,26 +649,21 @@  uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
             tci_write_reg(regs, t0, bswap32(t1));
             break;
 #endif
-#if TCG_TARGET_HAS_not_i32
-        case INDEX_op_not_i32:
+#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
+        CASE_32_64(not)
             t0 = *tb_ptr++;
             t1 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, ~t1);
             break;
 #endif
-#if TCG_TARGET_HAS_neg_i32
-        case INDEX_op_neg_i32:
+#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
+        CASE_32_64(neg)
             t0 = *tb_ptr++;
             t1 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, -t1);
             break;
 #endif
 #if TCG_TARGET_REG_BITS == 64
-        case INDEX_op_mov_i64:
-            t0 = *tb_ptr++;
-            t1 = tci_read_r(regs, &tb_ptr);
-            tci_write_reg(regs, t0, t1);
-            break;
         case INDEX_op_tci_movi_i64:
             t0 = *tb_ptr++;
             t1 = tci_read_i64(&tb_ptr);
@@ -802,20 +797,6 @@  uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
             tci_write_reg(regs, t0, bswap64(t1));
             break;
 #endif
-#if TCG_TARGET_HAS_not_i64
-        case INDEX_op_not_i64:
-            t0 = *tb_ptr++;
-            t1 = tci_read_r(regs, &tb_ptr);
-            tci_write_reg(regs, t0, ~t1);
-            break;
-#endif
-#if TCG_TARGET_HAS_neg_i64
-        case INDEX_op_neg_i64:
-            t0 = *tb_ptr++;
-            t1 = tci_read_r(regs, &tb_ptr);
-            tci_write_reg(regs, t0, -t1);
-            break;
-#endif
 #endif /* TCG_TARGET_REG_BITS == 64 */
 
             /* QEMU specific operations. */

[PULL,22/27] tcg/tci: Merge mov, not and neg operations

Commit Message

Patch