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[209.51.188.17]) by mx.google.com with ESMTPS id x126si6716854ybx.192.2021.03.06.13.44.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:44:45 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wrTToI++; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52650 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIej6-0003te-ID for patch@linaro.org; Sat, 06 Mar 2021 16:44:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56948) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIebH-000793-8P for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:39 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:41634) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIebF-0002z4-E7 for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:38 -0500 Received: by mail-pl1-x62e.google.com with SMTP id d11so3096268plo.8 for ; Sat, 06 Mar 2021 13:36:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rDTef7VWE7fxk2i0+V52DytmGBNiPfjpzsN2oBg9LYg=; b=wrTToI++D6HA53K6iBpU+sNuwARZQLQhkrLscFO7A30mHXtVIW5vpCDpUeNcFFYGw5 4JSe+i7PewtfuzG50PcAsDfZt6usyrTD+NG8kPCXzTmNTLCjwznSnU7+zPL7fcxXrSVs DxZLxBzR5NydOtTes/aHuXoZtNCog1owPvTyTXSmoB5FElOR9TmcOW6QtsCIASNjIl99 1UJTGhif97O7GOF1HMZDQhEqsVvHGC66BS4aERaeYRceQLEIykj9keW90PC55bMycSjU VVDmUtZqf7JxgtqgLx7fS6oLUPrHPckUEH60je5ZDETO81iRQKHRnGBVuEroh6CL7BQN FEfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rDTef7VWE7fxk2i0+V52DytmGBNiPfjpzsN2oBg9LYg=; b=q52KQU3+eqiE6ddHG5KSws6eevTE4wqcdlx68A3qwKsvmQqlYzkr+ffjFNCku1rwHl nFgvVklD1UkWA0fFd6W1JUzS65lhRAvT/ZU8+PcYUGLwlNbkW5RKpKAmA9oii8k+OZNw xNUyURR0XvA/sOz40poRkLjXqwogvYp2Oz1MfE4FKWsyTvzM4iq532jjsh/Ax9whh+TI Jiu5Mj1w0MZV6+iG3Gt0swD89GDFQcN8UN3tc80d4zHcOiinNcespp9W6okvTgMQe3qw tfbqXyqwytbdwjVQbtmmpPpm1JP5wnswCaNXrvvcZ3d4BSCZ+9ZaaQGdSG/BIL7A94v7 8bMQ== X-Gm-Message-State: AOAM532eYhbRoodm7TQcFO0VxPiP8KOwJW7iOtKGZylzXMCPWV9oLY0g IgkYsfCBF0s2b4tb3pmAIG2CteBA6oe3xg== X-Received: by 2002:a17:902:6944:b029:e6:190d:56cd with SMTP id k4-20020a1709026944b02900e6190d56cdmr41659plt.53.1615066595083; Sat, 06 Mar 2021 13:36:35 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 20/27] tcg/tci: Merge extension operations Date: Sat, 6 Mar 2021 13:36:06 -0800 Message-Id: <20210306213613.85168-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This includes ext8s, ext8u, ext16s, ext16u. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 44 ++++++++------------------------------------ 1 file changed, 8 insertions(+), 36 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index d0bf810781..73f639d23a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -607,29 +607,29 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS == 32 */ -#if TCG_TARGET_HAS_ext8s_i32 - case INDEX_op_ext8s_i32: +#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 + CASE_32_64(ext8s) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int8_t)t1); break; #endif -#if TCG_TARGET_HAS_ext16s_i32 - case INDEX_op_ext16s_i32: +#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 + CASE_32_64(ext16s) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int16_t)t1); break; #endif -#if TCG_TARGET_HAS_ext8u_i32 - case INDEX_op_ext8u_i32: +#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 + CASE_32_64(ext8u) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint8_t)t1); break; #endif -#if TCG_TARGET_HAS_ext16u_i32 - case INDEX_op_ext16u_i32: +#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 + CASE_32_64(ext16u) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint16_t)t1); @@ -779,34 +779,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, continue; } break; -#if TCG_TARGET_HAS_ext8u_i64 - case INDEX_op_ext8u_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint8_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext8s_i64 - case INDEX_op_ext8s_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int8_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext16s_i64 - case INDEX_op_ext16s_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int16_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext16u_i64 - case INDEX_op_ext16u_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint16_t)t1); - break; -#endif #if TCG_TARGET_HAS_ext32s_i64 case INDEX_op_ext32s_i64: #endif