From patchwork Sat Mar 6 21:36:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394563 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp551684jai; Sat, 6 Mar 2021 13:43:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJwiOaVv9UjBZMBFpfpLTy7pM2v611up9VQhgosIr6ilrcuLS6i/kCDU7OKVz24x0UX2Y/JI X-Received: by 2002:a92:c644:: with SMTP id 4mr14403048ill.237.1615067013149; Sat, 06 Mar 2021 13:43:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615067013; cv=none; d=google.com; s=arc-20160816; b=RX3zSMdETPCscZwpoS1fNsYI3JxWn1DVIDOSwOWnsdv8+0MbpM72dKlYoH5Dzp051D eLLEyT+f2NamcORV/9/LLm7UZ6vdQG+n+dsXRZJMK4gTMV4fR750nvx5BHQDPT/6UAe0 y4rhes4wfaiIpUFK4PvaaAAC/Ml7yjcBwjNoBO+hoJdlXEWdjZ84XGvUVfImF+d37pPL OJzRitmWxS9ObhaZHc7NQaHSCHBOn/Bb8zQGJTTd4KnkG2mbwyuGEbJjzhRhIZKlpBBi OHKPzTBEERfsgfFCC0nif+68hi5+ZoiSGIVEmiVuFYTIWBIFyC+p5KjH3pFr6oOgf8Ob u7vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RiZhAqk94IR59YM6JHo6AIRSs7mF45dtttOIiGxjJYA=; b=Uz/pW7wIiVQP2olFRzti8B6pMIJDLp9t2SSJxzAzsEphE8olziqDYL4uTp9r6BLp3C PrXP3vObCqULNsAMq77PVbPC9OVjXCoz4esWG6O3mIZAVYurv+c3odoySlFVrUWirkiH w1MASOrlj8S9B8uLM09+48ithfWxQdz9iVZK/DbeERYWJrHXVVL5E456Hjs9ecnhZkCT iBshVvQLjDpzbHRcgxkF6xbqW3vVLK7n9FpfWuC3I8ZJlx+4THYdLykvvwUqh+gLExS8 EwPDz1PJ1IEyWuLHzjJzDqCgNxcpyx5xEVcSQAISCZaFjWrYcItz7qnq4hPS/rTY2GDo RQ/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="y/1tpW/u"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a24si6612349iok.37.2021.03.06.13.43.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:43:33 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="y/1tpW/u"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIehw-0000Vq-DP for patch@linaro.org; Sat, 06 Mar 2021 16:43:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56918) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIebE-00070r-Fu for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:36 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:44607) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIeb9-0002yB-Tq for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:36 -0500 Received: by mail-pf1-x433.google.com with SMTP id t29so4532769pfg.11 for ; Sat, 06 Mar 2021 13:36:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RiZhAqk94IR59YM6JHo6AIRSs7mF45dtttOIiGxjJYA=; b=y/1tpW/uUerCLzXplE1PCE1vZikLTfUkQdnZ/TVreJRyqv4Bbo9mwwuTCEqI9M8CMS oAvKagOz7l1VkwVk66yW5LShvXauSQYIFwXlMwrYqd3iAJTKaLOz5QcmvUkVupsV6nSZ LJvJG9g/cGxv6Jji4VJyPx8mOI2qkHIvXNFhDKwSFJYMmaMyhaasx5OxegH3KGqO/fhT 4mB+ILKxIcBWN/M+BHBM5juBv7YNiVLcJ8VJ9miL4aS2ei7Myhhyb0JblLSH9VVyMj+L xQ+1isM+0uPsTsWwC0YMi96Fsqx9MBL87eCsE5jYl4q0gB+EQtFxSYJEGlQ1GxIs2vy5 cOAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RiZhAqk94IR59YM6JHo6AIRSs7mF45dtttOIiGxjJYA=; b=fZP8O70Bocpxg07w8tdWrK6W7MAkf0VaSv8WTFmyqPR0JtwpwdZg3KNzQN8afewXUa gpWcOo4WS1XlxSOEacgRvILOk+4/8HccTTj20zHruV8hsxrlOJzodCmLQIOr3xZEUL5M Pf85fVwUmrhEUhH7TI/MPdjUiYwzG4V61sJv3FGANfSW/HXy9una57etrB+TDt/VXrVf TKfXY0xOryzIk/Hr1JpeSGW891naMwWProw/4q7HbO8ioOR1qT3JChy9VT1rn+g0aZ3e CHAoaTufp9GBiQttlrhxEJ2616ThqG/nVcFaISfqATN5fYbpnZiCxQNMUs9SMfNQRxAI SmBw== X-Gm-Message-State: AOAM531A4qZUtdqkbO1eXlDPYl3xEOvuSpN3t1SY8jvVBl5PBFSYWiCS EjT9eHAoBQE5ww9FqE0sImKOS5qjH4kbXg== X-Received: by 2002:a63:1d26:: with SMTP id d38mr14705633pgd.385.1615066590593; Sat, 06 Mar 2021 13:36:30 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 15/27] tcg/tci: Remove tci_read_r16s Date: Sat, 6 Mar 2021 13:36:01 -0800 Message-Id: <20210306213613.85168-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use explicit casts for ext16s opcodes. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 26 ++++---------------------- 1 file changed, 4 insertions(+), 22 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 2440da1746..8b91e6efc3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) return regs[index]; } -#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int16_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_REG_BITS == 64 static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) { @@ -152,17 +145,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) return value; } -#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -/* Read indexed register (16 bit signed) from bytecode. */ -static int16_t tci_read_r16s(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - int16_t value = tci_read_reg16s(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} -#endif - /* Read indexed register (32 bit) from bytecode. */ static uint32_t tci_read_r32(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -671,8 +653,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext16s_i32 case INDEX_op_ext16s_i32: t0 = *tb_ptr++; - t1 = tci_read_r16s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 @@ -886,8 +868,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext16s_i64 case INDEX_op_ext16s_i64: t0 = *tb_ptr++; - t1 = tci_read_r16s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i64