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[209.51.188.17]) by mx.google.com with ESMTPS id l84si5064963ybf.274.2021.02.18.02.06.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Feb 2021 02:06:50 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EGLehANv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52704 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lCgCw-0003DW-61 for patch@linaro.org; Thu, 18 Feb 2021 05:06:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54268) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lCfzP-0004TT-OG for qemu-devel@nongnu.org; Thu, 18 Feb 2021 04:52:53 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:32819) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lCfzN-0000yh-MY for qemu-devel@nongnu.org; Thu, 18 Feb 2021 04:52:51 -0500 Received: by mail-wr1-x42f.google.com with SMTP id 7so2242379wrz.0 for ; Thu, 18 Feb 2021 01:52:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F+StAOu3qxmsqdNHe7+WWm/s4oEdZe+M8dtFdhw4Ux0=; b=EGLehANvZVsBQm4hPQacFnA76oHvnmNtigYjR/HNt4UQnkJ4z1KCrpaRk8zYGm0XEN RP+1ISPuUgfOktAfJLRFNn/At1CXSKGdghQkR5djZnyiNR6nWGx4ChrAqAC3lvvgQ2+J aaRF7u3bGZj8AN+pso7kgfwENlNNyctawK2sX+O23JXihz8WW64XS6PAiivT51AjWtOj WghQF5DAxNvUs50jCDQiF6xhiiC1OLaGOLBmmfCiP74Yu7i+Bx1bQDUClcgMFPwtTJs8 mGqdOOw1hm6cY8ac0WyWpXYybm/0OCyuk7sLRdsuuPDBrEnDsRnoHvAxvHzRr6tiWpZm OmcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F+StAOu3qxmsqdNHe7+WWm/s4oEdZe+M8dtFdhw4Ux0=; b=IGjTZMte7hECMhIEH+eaCbebAQdtU05vUrRl75irG/0qmphUrYTOrpqFu/fct4kS6x QpqtQpFNSymEnt12hp9vPoAgRPBC9i0S+o2OcQbmp1UfraZgk+EES0+RaZxNwATxfk4D bHOdi5Jx6HplTr1fcZVRlf+rx+5NPeD9n3v7Xh+GrJntnB/YVbarlXtx//Ism2clLma1 CK8Bg+SvRVvuecMDon0/K4K0oNMiqGc41R/2ABMjf0lFxSd9RcT4H5Rr6f4CWh0MRJwc rjMKl5jAYYVlW39/noKuU7NvC/GLLjWmqhRHtivWSOvqoVCIiqNXXavhP94aqz3iJtNs Q1xQ== X-Gm-Message-State: AOAM5339Holf1ynefjfxHpPPz+pUPKaOO6YwN0Sm2byXdNQWJPShHRAu buXvipevbxcYVRqZQgeDxLoMFg== X-Received: by 2002:adf:dcc2:: with SMTP id x2mr3331994wrm.178.1613641968028; Thu, 18 Feb 2021 01:52:48 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id y16sm7809783wrw.46.2021.02.18.01.52.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Feb 2021 01:52:46 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id BA52C1FF98; Thu, 18 Feb 2021 09:47:07 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Subject: [PULL 09/23] accel/tcg/plugin-gen: fix the call signature for inline callbacks Date: Thu, 18 Feb 2021 09:46:52 +0000 Message-Id: <20210218094706.23038-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210218094706.23038-1-alex.bennee@linaro.org> References: <20210218094706.23038-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , "Emilio G . Cota" , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org, Paolo Bonzini Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A recent change to the handling of constants in TCG changed the pattern of ops emitted for a constant add. We no longer emit a mov and the constant can be applied directly to the TCG_op_add arguments. This was causing SEGVs when running the insn plugin with arg=inline. Fix this by updating copy_add_i64 to do the right thing while also adding a comment at the top of the append section as an aide memoir if something like this happens again. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Cc: Emilio G. Cota Message-Id: <20210213130325.14781-10-alex.bennee@linaro.org> -- 2.20.1 diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index e5dc9d0ca9..8a1bb801e0 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -320,22 +320,6 @@ static TCGOp *copy_const_ptr(TCGOp **begin_op, TCGOp *op, void *ptr) return op; } -static TCGOp *copy_const_i64(TCGOp **begin_op, TCGOp *op, uint64_t v) -{ - if (TCG_TARGET_REG_BITS == 32) { - /* 2x mov_i32 */ - op = copy_op(begin_op, op, INDEX_op_mov_i32); - op->args[1] = tcgv_i32_arg(tcg_constant_i32(v)); - op = copy_op(begin_op, op, INDEX_op_mov_i32); - op->args[1] = tcgv_i32_arg(tcg_constant_i32(v >> 32)); - } else { - /* mov_i64 */ - op = copy_op(begin_op, op, INDEX_op_mov_i64); - op->args[1] = tcgv_i64_arg(tcg_constant_i64(v)); - } - return op; -} - static TCGOp *copy_extu_tl_i64(TCGOp **begin_op, TCGOp *op) { if (TARGET_LONG_BITS == 32) { @@ -374,14 +358,17 @@ static TCGOp *copy_st_i64(TCGOp **begin_op, TCGOp *op) return op; } -static TCGOp *copy_add_i64(TCGOp **begin_op, TCGOp *op) +static TCGOp *copy_add_i64(TCGOp **begin_op, TCGOp *op, uint64_t v) { if (TCG_TARGET_REG_BITS == 32) { /* all 32-bit backends must implement add2_i32 */ g_assert(TCG_TARGET_HAS_add2_i32); op = copy_op(begin_op, op, INDEX_op_add2_i32); + op->args[4] = tcgv_i32_arg(tcg_constant_i32(v)); + op->args[5] = tcgv_i32_arg(tcg_constant_i32(v >> 32)); } else { op = copy_op(begin_op, op, INDEX_op_add_i64); + op->args[2] = tcgv_i64_arg(tcg_constant_i64(v)); } return op; } @@ -431,6 +418,12 @@ static TCGOp *copy_call(TCGOp **begin_op, TCGOp *op, void *empty_func, return op; } +/* + * When we append/replace ops here we are sensitive to changing patterns of + * TCGOps generated by the tcg_gen_FOO calls when we generated the + * empty callbacks. This will assert very quickly in a debug build as + * we assert the ops we are replacing are the correct ones. + */ static TCGOp *append_udata_cb(const struct qemu_plugin_dyn_cb *cb, TCGOp *begin_op, TCGOp *op, int *cb_idx) { @@ -462,11 +455,8 @@ static TCGOp *append_inline_cb(const struct qemu_plugin_dyn_cb *cb, /* ld_i64 */ op = copy_ld_i64(&begin_op, op); - /* const_i64 */ - op = copy_const_i64(&begin_op, op, cb->inline_insn.imm); - /* add_i64 */ - op = copy_add_i64(&begin_op, op); + op = copy_add_i64(&begin_op, op, cb->inline_insn.imm); /* st_i64 */ op = copy_st_i64(&begin_op, op);