diff mbox series

[PULL,02/46] exec/cpu-defs: Remove TCG backends dependency

Message ID	20210205225650.1330794-3-richard.henderson@linaro.org
State	Accepted
Commit	37c8c531d61e34b69750aaeb61f7a0d5e9d9de3d
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 02/46] exec/cpu-defs: Remove TCG backends dependency Date: Fri, 5 Feb 2021 12:56:06 -1000 Message-Id: <20210205225650.1330794-3-richard.henderson@linaro.org> In-Reply-To: <20210205225650.1330794-1-richard.henderson@linaro.org> References: <20210205225650.1330794-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg patch queue \| expand [PULL,00/46] tcg patch queue [PULL,01/46] tcg/s390: Fix compare instruction from extended-immediate facility [PULL,02/46] exec/cpu-defs: Remove TCG backends dependency [PULL,03/46] tcg/aarch64: Do not convert TCGArg to temps that are not temps [PULL,04/46] configure: Fix --enable-tcg-interpreter [PULL,05/46] tcg/tci: Make tci_tb_ptr thread-local [PULL,06/46] tcg/tci: Implement INDEX_op_ld16s_i32 [PULL,07/46] tcg/tci: Implement INDEX_op_ld8s_i64 [PULL,08/46] tcg/tci: Inline tci_write_reg32s into the only caller [PULL,09/46] tcg/tci: Inline tci_write_reg8 into its callers [PULL,10/46] tcg/tci: Inline tci_write_reg16 into the only caller [PULL,11/46] tcg/tci: Inline tci_write_reg32 into all callers [PULL,12/46] tcg/tci: Inline tci_write_reg64 into 64-bit callers [PULL,13/46] tcg/tci: Merge INDEX_op_ld8u_{i32,i64} [PULL,14/46] tcg/tci: Merge INDEX_op_ld8s_{i32,i64} [PULL,15/46] tcg/tci: Merge INDEX_op_ld16u_{i32,i64} [PULL,16/46] tcg/tci: Merge INDEX_op_ld16s_{i32,i64} [PULL,17/46] tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64} [PULL,18/46] tcg/tci: Merge INDEX_op_st8_{i32,i64} [PULL,19/46] tcg/tci: Merge INDEX_op_st16_{i32,i64} [PULL,20/46] tcg/tci: Move stack bounds check to compile-time [PULL,21/46] tcg/tci: Merge INDEX_op_{st_i32,st32_i64} [PULL,22/46] tcg/tci: Use g_assert_not_reached [PULL,23/46] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_* [PULL,24/46] tcg/tci: Implement 64-bit division [PULL,25/46] tcg/tci: Remove TODO as unused [PULL,26/46] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16 [PULL,27/46] tcg/tci: Fix TCG_REG_R4 misusage [PULL,28/46] tcg/tci: Remove TCG_CONST [PULL,29/46] cpu: Introduce TCGCpuOperations struct [PULL,30/46] target/riscv: remove CONFIG_TCG, as it is always TCG [PULL,31/46] accel/tcg: split TCG-only code from cpu_exec_realizefn [PULL,32/46] cpu: Move synchronize_from_tb() to tcg_ops [PULL,33/46] cpu: Move cpu_exec_* to tcg_ops [PULL,34/46] cpu: Move tlb_fill to tcg_ops [PULL,35/46] cpu: Move debug_excp_handler to tcg_ops [PULL,36/46] target/arm: do not use cc->do_interrupt for KVM directly [PULL,37/46] cpu: move cc->do_interrupt to tcg_ops [PULL,38/46] cpu: move cc->transaction_failed to tcg_ops [PULL,39/46] cpu: move do_unaligned_access to tcg_ops [PULL,40/46] physmem: make watchpoint checking code TCG-only [PULL,41/46] cpu: move adjust_watchpoint_address to tcg_ops [PULL,42/46] cpu: move debug_check_watchpoint to tcg_ops [PULL,43/46] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass [PULL,44/46] accel: extend AccelState and AccelClass to user-mode [PULL,45/46] accel: replace struct CpusAccel with AccelOpsClass [PULL,46/46] accel: introduce AccelCPUClass extending CPUClass

Commit Message

Richard Henderson Feb. 5, 2021, 10:56 p.m. UTC

From: Philippe Mathieu-Daudé <f4bug@amsat.org>


"exec/cpu-defs.h" contains generic CPU definitions for the
TCG frontends (mostly related to TLB). TCG backends definitions
aren't relevant here.

See tcg/README description:

  4) Backend

  tcg-target.h contains the target specific definitions. tcg-target.c.inc
  contains the target specific code; it is #included by tcg/tcg.c, rather
  than being a standalone C file.

So far only "tcg/tcg.h" requires these headers.

Remove the "target-tcg.h" header dependency on TCG frontends, so we
don't have to rebuild all frontends when hacking a single backend.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-Id: <20210204191423.1754158-1-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 include/exec/cpu-defs.h | 3 ---
 1 file changed, 3 deletions(-)

-- 
2.25.1

diff mbox series

Patch

diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index d1f5e3fc3d..ba3cd32a1e 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -25,9 +25,6 @@ 
 
 #include "qemu/host-utils.h"
 #include "qemu/thread.h"
-#ifdef CONFIG_TCG
-#include "tcg-target.h"
-#endif
 #ifndef CONFIG_USER_ONLY
 #include "exec/hwaddr.h"
 #endif