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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id c23sm12155149pgc.72.2021.02.05.14.57.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 14:57:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 12/46] tcg/tci: Inline tci_write_reg64 into 64-bit callers Date: Fri, 5 Feb 2021 12:56:16 -1000 Message-Id: <20210205225650.1330794-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210205225650.1330794-1-richard.henderson@linaro.org> References: <20210205225650.1330794-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Note that we had two functions of the same name: a 32-bit version which took two register numbers and a 64-bit version which was a no-op wrapper for tcg_write_reg. After this, we are left with only the 32-bit version. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tci.c | 60 +++++++++++++++++++++++++------------------------------ 1 file changed, 27 insertions(+), 33 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 39ad00663f..0f56702b93 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -124,12 +124,6 @@ static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, tci_write_reg(regs, low_index, value); tci_write_reg(regs, high_index, value >> 32); } -#elif TCG_TARGET_REG_BITS == 64 -static void -tci_write_reg64(tcg_target_ulong *regs, TCGReg index, uint64_t value) -{ - tci_write_reg(regs, index, value); -} #endif #if TCG_TARGET_REG_BITS == 32 @@ -559,7 +553,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t1 = tci_read_r64(regs, &tb_ptr); t2 = tci_read_ri64(regs, &tb_ptr); condition = *tb_ptr++; - tci_write_reg64(regs, t0, tci_compare64(t1, t2, condition)); + tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; #endif case INDEX_op_mov_i32: @@ -839,12 +833,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_mov_i64: t0 = *tb_ptr++; t1 = tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i64: t0 = *tb_ptr++; t1 = tci_read_i64(&tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; /* Load/store operations (64 bit). */ @@ -886,7 +880,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); - tci_write_reg64(regs, t0, *(uint64_t *)(t1 + t2)); + tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st8_i64: t0 = tci_read_r8(regs, &tb_ptr); @@ -920,19 +914,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t0 = *tb_ptr++; t1 = tci_read_ri64(regs, &tb_ptr); t2 = tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 + t2); + tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 = *tb_ptr++; t1 = tci_read_ri64(regs, &tb_ptr); t2 = tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 - t2); + tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 = *tb_ptr++; t1 = tci_read_ri64(regs, &tb_ptr); t2 = tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 * t2); + tci_write_reg(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i64 case INDEX_op_div_i64: @@ -951,19 +945,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t0 = *tb_ptr++; t1 = tci_read_ri64(regs, &tb_ptr); t2 = tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 & t2); + tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 = *tb_ptr++; t1 = tci_read_ri64(regs, &tb_ptr); t2 = tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 | t2); + tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 = *tb_ptr++; t1 = tci_read_ri64(regs, &tb_ptr); t2 = tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 ^ t2); + tci_write_reg(regs, t0, t1 ^ t2); break; /* Shift/rotate operations (64 bit). */ @@ -972,32 +966,32 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t0 = *tb_ptr++; t1 = tci_read_ri64(regs, &tb_ptr); t2 = tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 << (t2 & 63)); + tci_write_reg(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 = *tb_ptr++; t1 = tci_read_ri64(regs, &tb_ptr); t2 = tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1 >> (t2 & 63)); + tci_write_reg(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 = *tb_ptr++; t1 = tci_read_ri64(regs, &tb_ptr); t2 = tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, ((int64_t)t1 >> (t2 & 63))); + tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 = *tb_ptr++; t1 = tci_read_ri64(regs, &tb_ptr); t2 = tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, rol64(t1, t2 & 63)); + tci_write_reg(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 = *tb_ptr++; t1 = tci_read_ri64(regs, &tb_ptr); t2 = tci_read_ri64(regs, &tb_ptr); - tci_write_reg64(regs, t0, ror64(t1, t2 & 63)); + tci_write_reg(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 @@ -1008,7 +1002,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tmp16 = *tb_ptr++; tmp8 = *tb_ptr++; tmp64 = (((1ULL << tmp8) - 1) << tmp16); - tci_write_reg64(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64)); + tci_write_reg(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64)); break; #endif case INDEX_op_brcond_i64: @@ -1026,28 +1020,28 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_ext8u_i64: t0 = *tb_ptr++; t1 = tci_read_r8(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 = *tb_ptr++; t1 = tci_read_r8s(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64 case INDEX_op_ext16s_i64: t0 = *tb_ptr++; t1 = tci_read_r16s(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i64 case INDEX_op_ext16u_i64: t0 = *tb_ptr++; t1 = tci_read_r16(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext32s_i64 @@ -1056,7 +1050,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_ext_i32_i64: t0 = *tb_ptr++; t1 = tci_read_r32s(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: @@ -1064,41 +1058,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_extu_i32_i64: t0 = *tb_ptr++; t1 = tci_read_r32(regs, &tb_ptr); - tci_write_reg64(regs, t0, t1); + tci_write_reg(regs, t0, t1); break; #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: t0 = *tb_ptr++; t1 = tci_read_r16(regs, &tb_ptr); - tci_write_reg64(regs, t0, bswap16(t1)); + tci_write_reg(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i64 case INDEX_op_bswap32_i64: t0 = *tb_ptr++; t1 = tci_read_r32(regs, &tb_ptr); - tci_write_reg64(regs, t0, bswap32(t1)); + tci_write_reg(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 = *tb_ptr++; t1 = tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t0, bswap64(t1)); + tci_write_reg(regs, t0, bswap64(t1)); break; #endif #if TCG_TARGET_HAS_not_i64 case INDEX_op_not_i64: t0 = *tb_ptr++; t1 = tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t0, ~t1); + tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i64 case INDEX_op_neg_i64: t0 = *tb_ptr++; t1 = tci_read_r64(regs, &tb_ptr); - tci_write_reg64(regs, t0, -t1); + tci_write_reg(regs, t0, -t1); break; #endif #endif /* TCG_TARGET_REG_BITS == 64 */