From patchwork Thu Feb 4 01:44:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 376178 Delivered-To: patch@linaro.org Received: by 2002:a17:906:48d2:0:0:0:0 with SMTP id d18csp909593ejt; Wed, 3 Feb 2021 18:13:57 -0800 (PST) X-Google-Smtp-Source: ABdhPJzCPG0i4pM+m4eO0qKOyPzAFiR/mHGoS/xK5PT5opWrx/B8DN7sV96Sn5rkRbNOuEKHoFlH X-Received: by 2002:a05:6902:100a:: with SMTP id w10mr8488073ybt.474.1612404836984; Wed, 03 Feb 2021 18:13:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612404836; cv=none; d=google.com; s=arc-20160816; b=Y+6/vg4Z2kFoktj3lcfRr+wwhgm6emDCvuUNIZSu5YLfseLybdchAOev8av6bCuQ3g WkN0imNO4naoBhNelzEq3Xtk7gm4QC4qmLJegKB8HsAIs4Mphwpvp4pmEXftXz7ODTIs t0sFNcinAf2y/sXy0qPyth+qiNVfIa6NCDl9dezF2Sm0pMHdTh5K6XuqWCTsXtkVFiq7 afFPGYpPrCcfKJ0Kg+bMMHnVWbI8472fLRy1Ip25iYsQcbCOzCvC2MkmjroceDE17pPi Pac4XysBgsv2/pNaUxmDzRVwMtEgcJ/rKLlKU2hvPelkLw3KtOXWawiJdV7e4PNYeS8K mFpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=b0OZ8HZNEJw4TVjXNMfY9ukiBorqmrftQz6h6YJ1/P4=; b=jDJd9Nl25vtHZn1JjbR0Kg7/0OwmMWLOYIgBXMsRZinT6vtW7VC6VsslL7HYQF2d29 ib0h4LhUbsl+CAqICHOJ2xaJUgvEGoXnxZZhk4zdUu85lLPOA++T9ieS6JsZ/B4trn7M 3fcRiQruC3lmTPOFHy9qnBJRy2rGUwaiHk312uMILhINlP1TanVwN9T2SDvJAJO+u7U7 oIjYnXnsb8r+VlxBKWapRpQ8/ri682BFyky77JRXBl52UntHbpTC9n6roBQLLozqr0Sx QQJ5SyxWXfkxirZPTC2u3KuRazsfHZeMw4m9csTXHdlAFQyqScL7Itrl87aKLiLAZu2N odCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JJNu6sHI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c131si4097185yba.383.2021.02.03.18.13.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Feb 2021 18:13:56 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JJNu6sHI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54006 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7U9c-0005Gb-Bj for patch@linaro.org; Wed, 03 Feb 2021 21:13:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44886) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7TjH-0005Ph-1K for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:43 -0500 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:43291) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l7Tiy-0003wu-7d for qemu-devel@nongnu.org; Wed, 03 Feb 2021 20:46:36 -0500 Received: by mail-pg1-x52e.google.com with SMTP id n10so1016116pgl.10 for ; Wed, 03 Feb 2021 17:46:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b0OZ8HZNEJw4TVjXNMfY9ukiBorqmrftQz6h6YJ1/P4=; b=JJNu6sHIoxvJg2SQXw3I2nYZ/AS0Nqi/b727N1o+HDijO2xALKqZ5ocBx3E0bMJdHh xq3eYZcKr3Cz6ZKFudiLPWEhS+3tkn6g28RNUSuTiuJCgMxn7lvpiGuIIBQeIqM+VP/n FhWoUi9/sEyhGirknOLFWPBZE7GmWJ8BjiXSApQ+gcuQVNMRKKcy2sDSQHk04Tn3Phnx VKiFPsDM3sv+B27HLjdI98FoHVit1dctxGXwwjcj+aNGIxcld6/613cqKSDUTvGP9T9F Dv4XlhXDo0qSfRAeV7VpZtimytg37V3pNYeQrPZma54Ukcl605bbxiOK4zJ6GaRH5zjS 39Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b0OZ8HZNEJw4TVjXNMfY9ukiBorqmrftQz6h6YJ1/P4=; b=NoZeSeTeUAe9ntedKeoaow+W0mTFq5r7Ra1nrgHuAzCicEddGAoJhwZIy2XPMPrtlY 5V+00lT7PgbJvI3vyukEfj7eOeVnGTMBYEJF7XFu45k3g1mg389a4SpUyG2mKikUqJVm IZrfnuxsRknrmIxun/4lGg55G7AxNAK5054GMa7YE3toJ6+jILBn7skKRCcxpeO38irq F97y6VxB3aSBLbSFPNAEs94JR115OgfQLGJdiiRsRSmL/lIrRB+yM6kWZT3fqmig1tCi n9Oej3iLs+yQ5cRUAY99PdkUMcllznbdVcDCnL3se3g2ApGAIMoUnR4vVeGxoCaWuxa4 DZ3w== X-Gm-Message-State: AOAM530iyz41hVvPzw81TcJdxrkA0OHR5r71r4PRdOOcb13j+NiG+XhA VSstcheAXLl0G36iVWX3IP9Wb3VUonEWPeuX X-Received: by 2002:a65:648e:: with SMTP id e14mr6492744pgv.453.1612403180967; Wed, 03 Feb 2021 17:46:20 -0800 (PST) Received: from localhost.localdomain (cpe-66-27-222-29.hawaii.res.rr.com. [66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.46.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:46:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 38/93] tcg/tci: Merge extension operations Date: Wed, 3 Feb 2021 15:44:14 -1000 Message-Id: <20210204014509.882821-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This includes ext8s, ext8u, ext16s, ext16u. Signed-off-by: Richard Henderson --- tcg/tci.c | 44 ++++++++------------------------------------ 1 file changed, 8 insertions(+), 36 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 894e87e1b0..cdfd9b7af8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -624,29 +624,29 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS == 32 */ -#if TCG_TARGET_HAS_ext8s_i32 - case INDEX_op_ext8s_i32: +#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 + CASE_32_64(ext8s) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int8_t)t1); break; #endif -#if TCG_TARGET_HAS_ext16s_i32 - case INDEX_op_ext16s_i32: +#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 + CASE_32_64(ext16s) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int16_t)t1); break; #endif -#if TCG_TARGET_HAS_ext8u_i32 - case INDEX_op_ext8u_i32: +#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 + CASE_32_64(ext8u) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint8_t)t1); break; #endif -#if TCG_TARGET_HAS_ext16u_i32 - case INDEX_op_ext16u_i32: +#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 + CASE_32_64(ext16u) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint16_t)t1); @@ -796,34 +796,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, continue; } break; -#if TCG_TARGET_HAS_ext8u_i64 - case INDEX_op_ext8u_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint8_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext8s_i64 - case INDEX_op_ext8s_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int8_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext16s_i64 - case INDEX_op_ext16s_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int16_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext16u_i64 - case INDEX_op_ext16u_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint16_t)t1); - break; -#endif #if TCG_TARGET_HAS_ext32s_i64 case INDEX_op_ext32s_i64: #endif