| Message ID | 20210204014509.882821-24-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show
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[66.27.222.29]) by smtp.gmail.com with ESMTPSA id q132sm3835462pfq.171.2021.02.03.17.45.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Feb 2021 17:45:55 -0800 (PST) From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH v2 23/93] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_* Date: Wed, 3 Feb 2021 15:43:59 -1000 Message-Id: <20210204014509.882821-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org> References: <20210204014509.882821-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: sw@weilnetz.de, =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org> |
| Series |
TCI fixes and cleanups
|
expand
|
diff --git a/tcg/tci.c b/tcg/tci.c index 36d594672f..25329345cf 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -652,7 +652,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_ri32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; -#if TCG_TARGET_HAS_div_i32 case INDEX_op_div_i32: t0 = *tb_ptr++; t1 = tci_read_ri32(regs, &tb_ptr); @@ -677,12 +676,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_ri32(regs, &tb_ptr); tci_write_reg(regs, t0, t1 % t2); break; -#elif TCG_TARGET_HAS_div2_i32 - case INDEX_op_div2_i32: - case INDEX_op_divu2_i32: - TODO(); - break; -#endif case INDEX_op_and_i32: t0 = *tb_ptr++; t1 = tci_read_ri32(regs, &tb_ptr); @@ -908,11 +901,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_remu_i64: TODO(); break; -#elif TCG_TARGET_HAS_div2_i64 - case INDEX_op_div2_i64: - case INDEX_op_divu2_i64: - TODO(); - break; #endif case INDEX_op_and_i64: t0 = *tb_ptr++; diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 82efb9af60..6dc5bac2f3 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -596,10 +596,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ TODO(); break; - case INDEX_op_div2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ - case INDEX_op_divu2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ - TODO(); - break; case INDEX_op_brcond_i64: tcg_out_r(s, args[0]); tcg_out_ri64(s, const_args[1], args[1]); @@ -639,10 +635,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_ri32(s, const_args[1], args[1]); tcg_out_ri32(s, const_args[2], args[2]); break; - case INDEX_op_div2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ - case INDEX_op_divu2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ - TODO(); - break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: